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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id i62sm22783375pfg.62.2016.08.25.12.52.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 Aug 2016 12:52:31 -0700 (PDT) From: Lina Iyer To: ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 16/16] ARM64: dts: Define CPU power domain for MSM8916 Date: Thu, 25 Aug 2016 13:51:46 -0600 Message-Id: <1472154706-40119-17-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472154706-40119-1-git-send-email-lina.iyer@linaro.org> References: <1472154706-40119-1-git-send-email-lina.iyer@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160825_125253_996009_2EFCE4F4 X-CRM114-Status: UNSURE ( 8.50 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, Juri.Lelli@arm.com, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, brendan.jackman@arm.com, sudeep.holla@arm.com, andy.gross@linaro.org, Lina Iyer MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Define power domain and the power states for the domain as defined by the PSCI firmware. The 8916 firmware supports OS initiated method of powering off the CPU clusters. Cc: Signed-off-by: Lina Iyer --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 3029773..506c712 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -64,6 +64,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + power-domains = <&CPU_PD>; }; CPU1: cpu@1 { @@ -73,6 +74,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + power-domains = <&CPU_PD>; }; CPU2: cpu@2 { @@ -82,6 +84,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + power-domains = <&CPU_PD>; }; CPU3: cpu@3 { @@ -91,6 +94,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; + power-domains = <&CPU_PD>; }; L2_0: l2-cache { @@ -107,12 +111,33 @@ min-residency-us = <2000>; local-timer-stop; }; + + CLUSTER_RET: cluster_retention { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: cluster_gdhs { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD: cpu-pd@0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>; + }; }; timer {