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[v2] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

Message ID 1472208482-30862-1-git-send-email-zhengxing@rock-chips.com (mailing list archive)
State New, archived
Headers show

Commit Message

zhengxing Aug. 26, 2016, 10:48 a.m. UTC
To rename "watchdog" to "watchdog0" explicitly for looking up.
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff840000

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly

 arch/arm64/boot/dts/rockchip/rk3399.dtsi |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Heiko Stübner Aug. 26, 2016, 11:14 a.m. UTC | #1
Am Freitag, 26. August 2016, 18:48:01 schrieb Xing Zheng:
> To rename "watchdog" to "watchdog0" explicitly for looking up.
> Dues to incorrect description in the TRM, the WDTs base address
> should be fixed and swap them like this:
> WDT0 - 0xff848000
> WDT1 - 0xff840000
> 
> And, it is right that only WDT0 can generate global software reset.
> We will update the TRM to fix it.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

I had applied v1 already, so I have now just amended it with the watchdog0
change [0]. In any case the fix is in my dts64 branch for 4.9 now.


Heiko


[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=8859d81a562e484f06712fadb8886d78ed0be851
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..1e714a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@ 
 		};
 	};
 
-	watchdog@ff840000 {
+	watchdog0@ff848000 {
 		compatible = "snps,dw-wdt";
-		reg = <0x0 0xff840000 0x0 0x100>;
+		reg = <0x0 0xff848000 0x0 0x100>;
 		clocks = <&cru PCLK_WDT>;
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 	};