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[2.238.57.164]) by smtp.gmail.com with ESMTPSA id d7sm24769353wjg.13.2016.08.27.06.44.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 27 Aug 2016 06:44:03 -0700 (PDT) From: Carlo Caione To: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux@endlessm.com, khilman@baylibre.com, mark.rutland@arm.com, matthias.bgg@gmail.com, narmstrong@baylibre.com, bjdooks@googlemail.com, srinivas.kandagatla@linaro.org Subject: [PATCH v3 6/6] ARM64: dts: amlogic: gxbb: Enable NVMEM Date: Sat, 27 Aug 2016 15:43:48 +0200 Message-Id: <1472305428-16874-7-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472305428-16874-1-git-send-email-carlo@caione.org> References: <1472305428-16874-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160827_144425_545407_ECFEC197 X-CRM114-Status: GOOD ( 10.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione Add the NVMEM device node in the DTSI. Signed-off-by: Carlo Caione --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 18 ++++++++++++++++++ drivers/firmware/meson/meson_sm.c | 3 ++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ca428e8..aea8fd6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -105,6 +105,24 @@ }; }; + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = #include #include +#include #include @@ -38,7 +39,7 @@ struct meson_sm_chip { }; struct meson_sm_chip gxbb_chip = { - .shmem_size = 0x1000, + .shmem_size = SZ_4K, .cmd_shmem_in_base = 0x82000020, .cmd_shmem_out_base = 0x82000021, .cmd = {