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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id yj6sm8153856pab.8.2016.08.30.14.09.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Aug 2016 14:09:33 -0700 (PDT) From: Bjorn Andersson To: Andy Gross Subject: [PATCH v2 2/2] arm64: dts: qcom: msm8916: Add Hexagon PIL node Date: Tue, 30 Aug 2016 14:09:30 -0700 Message-Id: <1472591370-20550-2-git-send-email-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1472591370-20550-1-git-send-email-bjorn.andersson@linaro.org> References: <1472591370-20550-1-git-send-email-bjorn.andersson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160830_140955_113280_B8A878EF X-CRM114-Status: GOOD ( 12.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Hexagon core on the msm8916 provides services for audio control, audio output, sensors and the Hexagon SDK. The Hexagon remoteproc node allows us to boot this core. Although its part of the core platform its left disabled as it will crash without the rmtfs QMI service and we do not yet handle crashes gracefully. Signed-off-by: Bjorn Andersson --- Changes since v1: - Rebase ontop of linux-next arch/arm64/boot/dts/qcom/msm8916.dtsi | 44 ++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5a1b5f5b3a90..f6df72da6c4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -77,7 +77,7 @@ no-map; }; - mpss@86800000 { + mpss_mem: mpss@86800000 { reg = <0x0 0x86800000 0x0 0x2b00000>; no-map; }; @@ -684,6 +684,48 @@ nvmem-cell-names = "calib", "calib_sel"; #thermal-sensor-cells = <1>; }; + + hexagon@4080000 { + compatible = "qcom,q6v5-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 24 1>, + <&hexagon_smp2p_in 0 0>, + <&hexagon_smp2p_in 1 0>, + <&hexagon_smp2p_in 2 0>, + <&hexagon_smp2p_in 3 0>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>; + clock-names = "iface", "bus", "mem"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + mx-supply = <&pm8916_l3>; + pll-supply = <&pm8916_l7>; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + }; }; smd {