From patchwork Mon Sep 5 16:31:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Punit Agrawal X-Patchwork-Id: 9314329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA28C60760 for ; Mon, 5 Sep 2016 16:35:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD5D528A2F for ; Mon, 5 Sep 2016 16:35:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B220A28A35; Mon, 5 Sep 2016 16:35:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 513DB28A2F for ; Mon, 5 Sep 2016 16:35:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bgwqf-0001r4-Ji; Mon, 05 Sep 2016 16:34:17 +0000 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140] helo=cam-smtp0.cambridge.arm.com) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bgwpL-0000y4-9D for linux-arm-kernel@lists.infradead.org; Mon, 05 Sep 2016 16:32:57 +0000 Received: from e105922-lin.cambridge.arm.com (e105922-lin.cambridge.arm.com [10.1.194.52]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with SMTP id u85GWXEa009229; Mon, 5 Sep 2016 17:32:33 +0100 Received: by e105922-lin.cambridge.arm.com (sSMTP sendmail emulation); Mon, 05 Sep 2016 17:32:33 +0100 From: Punit Agrawal To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [RFC v2 PATCH 7/7] arm64: KVM: Enable selective trapping of TLB instructions Date: Mon, 5 Sep 2016 17:31:37 +0100 Message-Id: <1473093097-30932-8-git-send-email-punit.agrawal@arm.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1473093097-30932-1-git-send-email-punit.agrawal@arm.com> References: <1473093097-30932-1-git-send-email-punit.agrawal@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160905_093255_853030_C179C970 X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Punit Agrawal , Will Deacon , Steven Rostedt , Ingo Molnar , Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The TTLB bit of Hypervisor Control Register (HCR_EL2) controls the trapping of guest TLB maintenance instructions. Taking the trap requires a switch to the hypervisor and is an expensive operation. Enable selective trapping of guest TLB instructions when the associated perf trace event is enabled for a specific virtual machine. Signed-off-by: Punit Agrawal Cc: Christoffer Dall Cc: Marc Zyngier --- arch/arm64/kvm/perf_trace.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/kvm/perf_trace.c b/arch/arm64/kvm/perf_trace.c index 8bacd18..f26da1d 100644 --- a/arch/arm64/kvm/perf_trace.c +++ b/arch/arm64/kvm/perf_trace.c @@ -17,6 +17,8 @@ #include #include +#include + typedef int (*perf_trace_callback_fn)(struct kvm *kvm, bool enable); struct kvm_trace_hook { @@ -24,7 +26,37 @@ struct kvm_trace_hook { perf_trace_callback_fn setup_fn; }; +static int tlb_invalidate_trap(struct kvm *kvm, bool enable) +{ + int i; + struct kvm_vcpu *vcpu; + + /* + * Halt the VM to ensure atomic update across all vcpus (this + * avoids racy behaviour against other modifications of + * HCR_EL2 such as kvm_toggle_cache/kvm_set_way_flush). + */ + kvm_arm_halt_guest(kvm); + kvm_for_each_vcpu(i, vcpu, kvm) { + unsigned long hcr = vcpu_get_hcr(vcpu); + + if (enable) + hcr |= HCR_TTLB; + else + hcr &= ~HCR_TTLB; + + vcpu_set_hcr(vcpu, hcr); + } + kvm_arm_resume_guest(kvm); + + return 0; +} + static struct kvm_trace_hook trace_hook[] = { + { + .key = "kvm_tlb_invalidate", + .setup_fn = tlb_invalidate_trap, + }, { }, };