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The controller is essentially a +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. We don’t expose all 256 mux inputs because the +documentation shows that upper part is not mapped to any pad. The actual number +of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : should be: "amlogic,meson8-gpio-intc” or + “amlogic,meson8b-gpio-intc” or “amlogic,gxbb-gpio-intc” +- interrupts : List of the GIC’s interrupts used as parent interrupts. + There should 8 of these interrupts. +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Exemple: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,gxbb-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; +};