From patchwork Wed Oct 19 15:21:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 9384499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 48E3A60487 for ; Wed, 19 Oct 2016 15:27:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3AC2528BB6 for ; Wed, 19 Oct 2016 15:27:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F7AE28C0B; Wed, 19 Oct 2016 15:27:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D732928BB6 for ; Wed, 19 Oct 2016 15:27:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwsjI-0001Lv-2V; Wed, 19 Oct 2016 15:24:32 +0000 Received: from mail-qt0-f174.google.com ([209.85.216.174]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwshs-0000GH-5B for linux-arm-kernel@lists.infradead.org; Wed, 19 Oct 2016 15:23:07 +0000 Received: by mail-qt0-f174.google.com with SMTP id q7so24194838qtq.1 for ; Wed, 19 Oct 2016 08:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0E8WnISw9vf1yQEJ1JxBE5VMlZi2lq2Rc0/aayslZ+s=; b=SsDT30axtoXg/yLMV4KVRpGB8HqpxDXG3dy3iNqYokWf4GfB9ieJmAqhGeOPavHjRp ieAJtz1hTvglSPJo2YtY3I3RAX6zyuKxQAacNbYHy+CIIZImmJgmMM8ZaUok3Befl2/e hMJ1bG/8OIGhvMHxkL7uKgsZsah8hgfB3GSrwSQCEvIVJQhSI/1mePTBSUNH4iWsq1NK y0Do5KxctGq5p35scweZ8ku0m/Tb+WCrUvjbh6/EfmBVNjo84MEFMKDi9Gv3gHhQicGW dB1o461RuloXGExptI4UhvJkiXgxPRwqSqCZ3iQe6sEhSOLtZ2SAd38Di4XSbN9/8hW6 2qzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0E8WnISw9vf1yQEJ1JxBE5VMlZi2lq2Rc0/aayslZ+s=; b=BKH5g/WuK93KAnMsk3LjP3KyqAYUrDcTSU/X7WVj5gGAxgCGKJ/7nL5lc7fOJp8wg7 BTrxZu7xpx4KCjD0NqlY/qG7RXX0P/kFtH1esY4ISnTPVvMEHZPNzbVeAoQpoInzoQeb 1ZItptSQsE8IydyIHyuPlstHpaut3v7EFUU6yS7nkTe24FdSc4D0OhlmB+h5DdU5L4lu v/SrqWhZ3NDW0eIITeOr9qUJwkRKu3eY03aVG7B2lYGdFlLxPKrol33esHrJZWeqOBTg IrD3DuNDpDkWtkq7/SV9NxuFOS4iNXqV6xuZ2lvmqbRQxkXSCLaetMOJQOFSjralck6h 769w== X-Gm-Message-State: AA6/9RlZ/BiImghV2+vpjnjF+IWTAQFb0pJLE5xQ6aTzq0/p9Wr7XehV6b553bOhfrlc/enq X-Received: by 10.28.22.17 with SMTP id 17mr5304620wmw.128.1476890497227; Wed, 19 Oct 2016 08:21:37 -0700 (PDT) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f2sm69725653wjr.2.2016.10.19.08.21.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 08:21:36 -0700 (PDT) From: Jerome Brunet To: Carlo Caione , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Subject: [PATCH v2 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller Date: Wed, 19 Oct 2016 17:21:13 +0200 Message-Id: <1476890480-8884-3-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476890480-8884-1-git-send-email-jbrunet@baylibre.com> References: <1476890480-8884-1-git-send-email-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161019_082304_500171_4DD8478B X-CRM114-Status: GOOD ( 16.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Catalin Marinas , Linus Walleij , Will Deacon , linux-kernel@vger.kernel.org, Russell King , linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8, meson8b and gxbb SoC families Signed-off-by: Jerome Brunet --- Rob, I did not include the Ack you gave for the RFC as bindings have slightly changed. Only the interrupt property has be removed following a discussion I had with Marc .../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..2464d9a0865d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,31 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able watch the SoC pads +and generate an interrupt on edges or level. The controller is essentially a +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. We don’t expose all 256 mux inputs because the +documentation shows that upper part is not mapped to any pad. The actual number +of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : should be either + "amlogic,meson8-gpio-intc” for meson8 SoCs (AML7826MX) or + “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or + “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Example: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; +};