From patchwork Thu Oct 20 01:15:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 9385727 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6014E60487 for ; Thu, 20 Oct 2016 01:15:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5087B296EF for ; Thu, 20 Oct 2016 01:15:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 42B3929703; Thu, 20 Oct 2016 01:15:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A91F9296EF for ; Thu, 20 Oct 2016 01:15:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bx1vr-0005Nw-4g; Thu, 20 Oct 2016 01:14:07 +0000 Received: from conuserg-09.nifty.com ([210.131.2.76]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bx1vX-0005K3-Oi for linux-arm-kernel@lists.infradead.org; Thu, 20 Oct 2016 01:13:48 +0000 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id u9K1D0sf008597; Thu, 20 Oct 2016 10:13:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com u9K1D0sf008597 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476925982; bh=aenWBcgN1Qg3BuwDqpLCkf3tvLCaWYuAE3mETGw9Lkg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0aQ3z3jSdTkmaGmU/tcGs+reW340utXgiZoJB2ZSZf7Clg4ChtnKPSEkjqDRkp7Tr ffDDL9ToCm9TfP7TIMIG4ibPeO6Qx6XpPqyo345Z7EPw1Igyp/kVApb8jx/es7zCcQ BYI3Jf3P1DYmk7dg7RQo26OoeQDr9iMaeOBI/Faml7OoZQPJPuZwUgiSUiiJNERAA5 hZ6gzLzMoRXsNcaBl1NGXzrT2xAPzjQv6OhTLC/BYdQnIRu66qgoQRc2LtmGLx1P0v wH1uOGhdek5LU11ixb8vVWhM5CgRbWTXsdJxn8e7YMwCbAQcepfksdCrzeRQdvF1uF lxnJ+iefjE1UA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Date: Thu, 20 Oct 2016 10:15:26 +0900 Message-Id: <1476926126-6079-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476926126-6079-1-git-send-email-yamada.masahiro@socionext.com> References: <1476926126-6079-1-git-send-email-yamada.masahiro@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161019_181348_096744_BC5F9025 X-CRM114-Status: UNSURE ( 9.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Viresh Kumar , Will Deacon , linux-kernel@vger.kernel.org, Masahiro Yamada , Rob Herring , Catalin Marinas MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada --- Changes in v2: - Match the node name to the opp-hz property. arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 6f48e82..7404678 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -79,28 +79,36 @@ device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; }; @@ -109,6 +117,82 @@ method = "smc"; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666666666 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733333333 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + clocks { refclk: ref { compatible = "fixed-clock";