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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id s133sm3095768wmd.19.2016.10.21.02.08.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Oct 2016 02:08:17 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@stlinux.com, patrice.chotard@st.com Subject: [PATCH] ARM: sti: stih407-clocks: Identify critical clocks Date: Fri, 21 Oct 2016 10:08:11 +0100 Message-Id: <1477040891-31611-1-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161021_020840_717949_ADB56B50 X-CRM114-Status: GOOD ( 10.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.griffin@linaro.org, lee.jones@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover is to restart the board(s). This driver takes references to clocks which are required to be always-on. The Common Clk Framework will then take references to them. This way they will not be turned off during the clk_disabled_unused() procedure. In this patch we are identifying clocks, which if gated would render the STiH407 development board unserviceable. Signed-off-by: Peter Griffin Acked-by: Patrice Chotard --- arch/arm/boot/dts/stih407-clock.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 13029c0..34c119a 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -101,6 +101,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +113,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = ; }; }; @@ -126,6 +128,7 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; clk_s_c0: clockgen-c@09103000 { @@ -139,6 +142,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +198,12 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = , + , + , + , + , + ; }; };