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Tue, 25 Oct 2016 12:33:39 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD037.mail.protection.outlook.com (10.58.144.100) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.679.5 via Frontend Transport; Tue, 25 Oct 2016 12:33:38 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.63]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u9PCXY8T029187; Tue, 25 Oct 2016 05:33:34 -0700 From: Minghuan Lian To: , , Subject: [PATCH 1/6] dt/bindings: adjust bindings for Layerscape SCFG MSI Date: Tue, 25 Oct 2016 20:35:40 +0800 Message-ID: <1477398945-22774-1-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131218724192084629; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0301MB1618 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161025_053402_132386_C936008A X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Stuart Yoder , Yang-Leo Li , Minghuan Lian , Scott Wood , Shawn Guo , Mingkai Hu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 1. The different version of a SoC may have different MSI implementation. But compatible "fsl,-msi" can not describe the SoC version. The MSI driver will use SoC match interface to get SoC type and version instead of compatible string. So all MSI node can use the common compatible "fsl,ls-scfg-msi" and the original compatible is unnecessary. 2. Layerscape SoCs may have one or several MSI controllers. In order to increase MSI interrupt number of a PCIe, the patch moves all MSI node into the parent node "msi-controller". So a PCIe can request MSI from all the MSI controllers. Signed-off-by: Minghuan Lian --- .../interrupt-controller/fsl,ls-scfg-msi.txt | 57 +++++++++++++++++++--- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt index 9e38949..29f95fd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -1,18 +1,28 @@ * Freescale Layerscape SCFG PCIe MSI controller +Layerscape SoCs may have one or multiple MSI controllers. +Each MSI controller must be showed as a child node. + Required properties: -- compatible: should be "fsl,-msi" to identify - Layerscape PCIe MSI controller block such as: - "fsl,1s1021a-msi" - "fsl,1s1043a-msi" +- compatible: should be "fsl,ls-scfg-msi" +- #address-cells: must be 2 +- #size-cells: must be 2 +- ranges: allows valid 1:1 translation between child's address space and + parent's address space - msi-controller: indicates that this is a PCIe MSI controller node + +Required child node: +A child node must exist to represent the MSI controller. +The following are properties specific to those nodes: + - reg: physical base address of the controller and length of memory mapped. - interrupts: an interrupt to the parent interrupt controller. Optional properties: - interrupt-parent: the phandle to the parent interrupt controller. +Notes: This interrupt controller hardware is a second level interrupt controller that is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based platforms. If interrupt-parent is not provided, the default parent interrupt @@ -22,9 +32,40 @@ MSI controller node Examples: - msi1: msi-controller@1571000 { - compatible = "fsl,1s1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>, + msi: msi-controller { + compatible = "fsl,ls-scfg-msi"; + #address-cells = <2>; + #size-cells = <2>; + ranges; msi-controller; - interrupts = <0 116 0x4>; + + msi0@1580000 { + reg = <0x0 0x1580000 0x0 0x10000>; + interrupts = <0 116 0x4>, + <0 111 0x4>, + <0 112 0x4>, + <0 113 0x4>; + }; + + msi1@1590000 { + reg = <0x0 0x1590000 0x0 0x10000>; + interrupts = <0 126 0x4>, + <0 121 0x4>, + <0 122 0x4>, + <0 123 0x4>; + }; + + msi2@15a0000 { + reg = <0x0 0x15a0000 0x0 0x10000>; + interrupts = <0 160 0x4>, + <0 155 0x4>, + <0 156 0x4>, + <0 157 0x4>; + }; + }; + + pcie@3400000 { + ... + msi-parent = <&msi>; + ... };