From patchwork Tue Oct 25 16:25:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 9395031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 020EE6077F for ; Tue, 25 Oct 2016 16:31:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E7DF128DE6 for ; Tue, 25 Oct 2016 16:31:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DCB552951C; Tue, 25 Oct 2016 16:31:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C2FFE28DE6 for ; Tue, 25 Oct 2016 16:31:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bz4bp-0004ks-P5; Tue, 25 Oct 2016 16:29:53 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bz4Yc-0002JK-7H for linux-arm-kernel@lists.infradead.org; Tue, 25 Oct 2016 16:26:44 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u9PGB3kL019779; Tue, 25 Oct 2016 18:25:53 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 267w85p2uq-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 25 Oct 2016 18:25:53 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E80B33A; Tue, 25 Oct 2016 16:25:52 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C2FCC2A6B; Tue, 25 Oct 2016 16:25:52 +0000 (GMT) Received: from localhost (10.48.0.167) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 25 Oct 2016 18:25:52 +0200 From: Fabrice Gasnier To: , , , Subject: [PATCH 05/10] iio: adc: stm32: add trigger polarity ext attr Date: Tue, 25 Oct 2016 18:25:17 +0200 Message-ID: <1477412722-24061-6-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477412722-24061-1-git-send-email-fabrice.gasnier@st.com> References: <1477412722-24061-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.0.167] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-10-25_15:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161025_092634_833846_B1DCCD19 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lars@metafoo.de, alexandre.torgue@st.com, pmeerw@pmeerw.net, linux@armlinux.org.uk, robh+dt@kernel.org, mcoquelin.stm32@gmail.com, knaack.h@gmx.de, fabrice.gasnier@st.com, jic23@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add trigger polarity extended attribute. Signed-off-by: Fabrice Gasnier --- drivers/iio/adc/stm32/stm32-adc.c | 41 ++++++++++++++++++++++++++++++++++++- drivers/iio/adc/stm32/stm32-adc.h | 4 ++++ drivers/iio/adc/stm32/stm32f4-adc.c | 12 +++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/stm32/stm32-adc.c b/drivers/iio/adc/stm32/stm32-adc.c index 1a13450..9b4b459 100644 --- a/drivers/iio/adc/stm32/stm32-adc.c +++ b/drivers/iio/adc/stm32/stm32-adc.c @@ -207,7 +207,11 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev, /* trigger source */ extsel = trig_info[ret].extsel; - exten = STM32_EXTEN_HWTRIG_RISING_EDGE; + + /* default to rising edge if no polarity */ + if (adc->exten == STM32_EXTEN_SWTRIG) + adc->exten = STM32_EXTEN_HWTRIG_RISING_EDGE; + exten = adc->exten; } spin_lock_irqsave(&adc->lock, flags); @@ -221,6 +225,40 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev, return 0; } +static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int type) +{ + struct stm32_adc *adc = iio_priv(indio_dev); + + adc->exten = type; + + return 0; +} + +static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct stm32_adc *adc = iio_priv(indio_dev); + + return adc->exten; +} + +static const char * const stm32_trig_pol_items[] = { + [STM32_EXTEN_SWTRIG] = "swtrig", + [STM32_EXTEN_HWTRIG_RISING_EDGE] = "rising-edge", + [STM32_EXTEN_HWTRIG_FALLING_EDGE] = "falling-edge", + [STM32_EXTEN_HWTRIG_BOTH_EDGES] = "both-edges", +}; + +const struct iio_enum stm32_adc_trig_pol = { + .items = stm32_trig_pol_items, + .num_items = ARRAY_SIZE(stm32_trig_pol_items), + .get = stm32_adc_get_trig_pol, + .set = stm32_adc_set_trig_pol, +}; +EXPORT_SYMBOL_GPL(stm32_adc_trig_pol); + /** * stm32_adc_conv_irq_enable() - Unmask end of conversion irq * @adc: stm32 adc instance @@ -893,6 +931,7 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, chan->scan_type.realbits = adc->common->data->highres; chan->scan_type.storagebits = STM32_STORAGEBITS; chan->scan_type.shift = 0; + chan->ext_info = adc->common->data->ext_info; } static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, diff --git a/drivers/iio/adc/stm32/stm32-adc.h b/drivers/iio/adc/stm32/stm32-adc.h index fe3568b..6c9b70d 100644 --- a/drivers/iio/adc/stm32/stm32-adc.h +++ b/drivers/iio/adc/stm32/stm32-adc.h @@ -234,6 +234,7 @@ struct stm32_adc_reginfo { * @ext_triggers: Reference to trigger info for regular channels * @jext_triggers: Reference to trigger info for injected channels * @adc_reginfo: stm32 ADC registers description + * @ext_info: Extended channel info * @highres: Max resolution * @max_clock_rate: Max input clock rate * @clk_sel: routine to select common clock and prescaler @@ -251,6 +252,7 @@ struct stm32_adc_ops { const struct stm32_adc_trig_info *ext_triggers; const struct stm32_adc_trig_info *jext_triggers; const struct stm32_adc_reginfo *adc_reginfo; + const struct iio_chan_spec_ext_info *ext_info; int highres; unsigned long max_clock_rate; int (*clk_sel)(struct stm32_adc *adc); @@ -273,6 +275,7 @@ struct stm32_adc_ops { * @id: ADC instance number (e.g. adc 1, 2 or 3) * @offset: ADC instance register offset in ADC block * @max_channels: Max channels number for this ADC. + * @exten: External trigger config (enable/polarity) * @extrig_list: External trigger list (for regular channel) * @completion: end of single conversion completion * @buffer: data buffer @@ -295,6 +298,7 @@ struct stm32_adc { int id; int offset; int max_channels; + enum stm32_adc_exten exten; struct list_head extrig_list; struct completion completion; u16 *buffer; diff --git a/drivers/iio/adc/stm32/stm32f4-adc.c b/drivers/iio/adc/stm32/stm32f4-adc.c index 4d7a2a8..e033a68 100644 --- a/drivers/iio/adc/stm32/stm32f4-adc.c +++ b/drivers/iio/adc/stm32/stm32f4-adc.c @@ -555,11 +555,23 @@ static int stm32f4_adc_clk_sel(struct stm32_adc *adc) return 0; } +static const struct iio_chan_spec_ext_info stm32f4_adc_ext_info[] = { + IIO_ENUM("trigger_pol", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), + { + .name = "trigger_pol_available", + .shared = IIO_SHARED_BY_ALL, + .read = iio_enum_available_read, + .private = (uintptr_t)&stm32_adc_trig_pol, + }, + {}, +}; + static const struct stm32_adc_ops stm32f4_adc_ops = { .adc_info = stm32f4_adc_info, .ext_triggers = stm32f4_adc_ext_triggers, .jext_triggers = stm32f4_adc_jext_triggers, .adc_reginfo = &stm32f4_adc_reginfo, + .ext_info = stm32f4_adc_ext_info, .highres = 12, .max_clock_rate = 36000000, .clk_sel = stm32f4_adc_clk_sel,