From patchwork Tue Nov 8 05:56:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 9416635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 95D6360512 for ; Tue, 8 Nov 2016 05:59:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 858DB28BD2 for ; Tue, 8 Nov 2016 05:59:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 79A6328BDD; Tue, 8 Nov 2016 05:59:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 999AC28BD2 for ; Tue, 8 Nov 2016 05:59:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3zQ2-00057i-5u; Tue, 08 Nov 2016 05:58:02 +0000 Received: from mail-bn3nam01on0064.outbound.protection.outlook.com ([104.47.33.64] helo=NAM01-BN3-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3zPY-0004zZ-69 for linux-arm-kernel@lists.infradead.org; Tue, 08 Nov 2016 05:57:36 +0000 Received: from BN3PR0301CA0011.namprd03.prod.outlook.com (10.160.180.149) by DM5PR03MB2891.namprd03.prod.outlook.com (10.175.106.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.707.6; Tue, 8 Nov 2016 05:57:10 +0000 Received: from BN1BFFO11FD050.protection.gbl (2a01:111:f400:7c10::1:127) by BN3PR0301CA0011.outlook.office365.com (2a01:111:e400:4000::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.707.6 via Frontend Transport; Tue, 8 Nov 2016 05:57:10 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD050.mail.protection.outlook.com (10.58.145.5) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.707.3 via Frontend Transport; Tue, 8 Nov 2016 05:57:04 +0000 X-IncomingTopHeaderMarker: OriginalChecksum:; UpperCasedChecksum:; SizeAsReceived:983; Count:10 Received: from b29397-desktop.ap.freescale.net (b29397-desktop.ap.freescale.net [10.192.242.114]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id uA85umV1008967; Mon, 7 Nov 2016 22:56:59 -0700 From: Peter Chen To: , , Subject: [PATCH v2 3/3] clk: imx: clk-imx6ul: add clk support for imx6ull Date: Tue, 8 Nov 2016 13:56:54 +0800 Message-ID: <1478584614-12054-4-git-send-email-peter.chen@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478584614-12054-1-git-send-email-peter.chen@nxp.com> References: <1478584614-12054-1-git-send-email-peter.chen@nxp.com> X-IncomingHeaderCount: 10 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131230582292385467; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.158.2; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(4326007)(305945005)(8666005)(33646002)(7416002)(105606002)(5660300001)(86362001)(626004)(47776003)(50226002)(5001770100001)(8676002)(81166006)(6666003)(356003)(81156014)(7846002)(2201001)(586003)(104016004)(92566002)(69596002)(36756003)(50466002)(8936002)(48376002)(77096005)(87936001)(2906002)(50986999)(5003940100001)(2950100002)(189998001)(76176999)(97736004)(106466001)(229853001)(85426001)(68736007)(7059030)(32563001)(2101003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR03MB2891; H:az84smr01.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD050; 1:UEvXO+MmXRmxDzGulesq9Z6nBM7EVWDmiIfbwW9EwwP13oeX+1YRIbZ/YQmlUwt1l/Z6JQnJXnmYG5RJdUXJEKm62YosDcec2kRVMWlMW6dvvQzaP7hwBjlRj4g2A0ar5PQ0M/qUqJG5b+V0Lan8mHgV5IMBGSjWaUin7tFjy/pn+QpEc41QGXUMVy8NFKz/A9BJMR/G9kApcet3QrrCZDYzMM6+365hKlWEnDgBBQhvRUu+UvJlWuMRBnE64fLx04c057G6sx16P7i8WBxQhAGL8uyKChCd24g9xqikkk07xnzAZRU6E0AXr4d8p2GhRUJPPBF1TCoY97WNG3zirhbDA/+ZQR9UXYs3jjnMLgqDdt/RbpZrBi+C9cCgKlylvkVgsBOfe6BzjMNZ6icq/c2JiOFVuKtkuaU6BJ8pSxQ4gqKkXTWv4/ykHGYVR6cLLCDjSdhlzPnR36+0yXxBBkSO5mkzfqth9GU+OVY6/Hy+ixmZ09MeKlRQNSMc6vI1Vko2oR2/cwCLQaXVimTYRbmJzrXhBcnBRsgf9nxS4fvT6lT4D9FHF6EKuUm9w6a/d7SKI5P2bnEHnBc37C0S8bOofELX23HHs9WUpJq/8FSzffmwJsD0NCdXiWXj69gfIqx4+1/E0BBei+O3FSrrFwRZoW4c3WwkxpoxBBN7IZMkKd0v4Pas3IdHy4sibFNi4Z+J5Ptg2xK6hdQDYn2KykZq5RhnRnegQg5TEGlYs0iX5PQRbbtQV6QRJhoccG5OFiytVGDdQo44U67rha/rym3y3SB/ZlCSGO9nyVTpklM= MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 8f6b88f9-9c7c-4c1f-8ebb-08d4079c13ab X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2891; 2:YTG1IzjkOJntyhIkoGK+54FF14Gl8NFQlLGOf/ozNs7eBCmTAb5hZCbO0WHq1i/jtbqqIJzfj0uJHxN3dDw2xq5g13iWvnNeC9oIxq7uOxA2uAk46jYFb6hNaiOnDwZK1jo8HynmQrY7q7XH/A1yBhtigRFVY0NICWFJTnIX0gui9xbj3pWdgbk2RMxLAoNUCWy4G/yi3IQqtOads/BRMw==; 3:l4o7gDUJqb/aazOjzEsMbCABnpCCRicuvK27pWQXi3x/ktkoQm6sZ1Zo2JjRsKA7moufo+0p3ni/FigkloHDW1/tR93Obg35f7RKEnppdsf82ZAofAOEbGITQyqhajUGg5GwfLUr5QzFAsN7pMZ7Xgf6U34LBQnqf1C5d887sY4sVyMdKvMR79KqYBU7ZNBsgjaWn7mhFJRRxWKgrbOeIP7vH/e9d3JQfrpV0jTDjFKTXZ/RyxseiXl/OkGGdYcV X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR03MB2891; X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2891; 25:HlZi9tiuEJvBaMFbBac/2AFWKfsSDOYE1/RJvYRptlJmHBu2Z4VARBXMIvahiIFttWY3XBOlPRNl65f3iKEsUAqD1AFFSOZ9YZSUnZLJT/VWmubUUJwqIjKyZ1DzoPXDBHxzqX8hjHQ7hCEwZw5h8rjhmaUHeTpF5hSVirnN6qGXHEPLDww8AIN1ABHfoHfiRVCfOHjANA2uiwnrK304oqIqcokQUISzZ0oGYYpdsxu6NZ+xp/C6EfGQqaZA4UQo5lgtBYVKUtPtsHsJLpgyKiG7oy/NtCkjk4V8htY0+eCTYS4GzSgigzGbYMAa8ny0Q9mNr5DzOnzd2RbztBDewwdp3j+UzC2X0pBdKgWr0cb1j1CDRCxvihOf6xsPTFRw4PWJ97w0+lRig5kQfFkCl5LeNHjdtfQ/h8SQCcJJlJ2FDxwnVDTh3mY0YZolGWwqofIqHstSvOa4NWQCArDhQibD7pTHtQVvQOXwleUI6YKeq+UjwHoPkPXK8dYqehHul7U3t0yxunFoEk8L8qyzD+DqnzDYvQVonP3hN9vPZTrLuIJ4s4SMZPB9s/rjzI1WoCr6AHG5XGH1m7r7yeAJA6L698o0ShX6WmoWH4bA8a1g/OTcd0Wd0do8EB+WFlVFYfAUEbALNmLmk7i+UETlovso+QvCz+owLMkdB6Gy2cgyTOW4X3sZHF7Gb8LD8l7QuX658sPZMI0ZAq3pdw+GZIh5GFd6rqaIXm55E+soHTVl4/BM3fXD8MJhB4qZhPtsRQ7uxD691K3SCfDuvsqICw== X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2891; 31:wYMUrdmUJz8lZg8gxN51/7eBxyeu4jsBVnhFS4DrpsyHBnWGnYvTucbXbBShETbaSTmDWZ5VYT+XQyiPZcV8BcSOewDo5tCccdmKHmh6WcUXR/j5cdfxo/uyQK6I8rbj6Fw6H5Ey7tCyoaawgqPoO1OcoWH7VLLmF1gTQykb5BshOL7opPAJF6JLXgc09lZ437DRu6RZUGaZ+vcwNQQdblJ2frJHwiuMz8/XkKcJ9gBoLhusLzVlAzbcL7NcsfbWkkB3f43MYTOqCsPMwvrFWg==; 4:ABLb/IheTuwRaBsJFIv5RF04JlECbPxV5a1BCBUwlujrIY7zbPn2hUrsE/V2C3OSchH2a3WhKU6mfHMh1jslPI6HSj10YrQr5zmythz7twq+oCsYXKeR015S+0FniJvNEFy/GcAqPk8obp3RNsIWmleQ5LOrCUz8XPiOs5v625t99eNmHUZAmuDx+GcUaC1GrsaG0YVNPGnR0XelrxMS+uic/h4FzlRd+netvvlUHNbuWPlryaEHZNl5Zcd3u+rNYt6ZTV050/ZkIb5cTDEExw/amCUsgnyU4RmGlwWRtnc6zugbjnVwDL1hs1QCXVe+L31ykorM0Uf2gzMoyLMne/DKnEGXrsIHR6ezZk/Dxo004W1+uHMDFbJArXqYbdMpSGle58qwSL54e4wVJ4X3g/Z9UEWw6CcUF2regHxYAz7EV7+2fTz5OIZ/3uwsTHHYWeWGI3sMXWcTnun1JxR8DTdmq/2gF9fRdhyw5BTvkNhSH1ODKwvUQuS25zK+xM3SZg4FZ9IcCgQVVIo1vORmunZujexwcV9Oxwmdcoe5o0oxQbsWiaZdqk57XFLxNBUw X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(13023025)(13024025)(13018025)(13017025)(8121501046)(5005006)(13015025)(3002001)(10201501046)(6055026); SRVR:DM5PR03MB2891; BCL:0; PCL:0; RULEID:(400006); SRVR:DM5PR03MB2891; X-Forefront-PRVS: 01208B1E18 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR03MB2891; 23:GYceGodnO06INd1V+Zk9kUzeNyZGUD3ACGRbshB4h?= =?us-ascii?Q?yCq+JIgq8VDAQozaEmjX+mXDSWCVSbWWuHbVLmqXh0SYdD2tjT9pvsbck5vN?= =?us-ascii?Q?qwXYOVbrJZwFg7K3STz8go0dmm/l9WhuHRM2VdnlD8Lh7EmmmAO00ar8GGGt?= =?us-ascii?Q?iCXGycIsB/4+Yf1ym/EQ8Jh9ur4O2EbOXChH0Rz+dq21i34qzAH6RUR6su87?= =?us-ascii?Q?Qoa3cPTVEUXaWMdHH6TPXVyk4kK33dARcMAD7zrqzWXE4tHH81X4Xv6mGMYX?= =?us-ascii?Q?dxGOoIJ2XMQ0JBPgtAdCVijghZBXRTrHR45yHmko10sfBWSdQIhRYc7dNlgD?= =?us-ascii?Q?mriygT/at96efu4sKkLB1U8XsKNMmlc/02V+YJ9XOmSPtPbxV5aAFr25LPp1?= =?us-ascii?Q?uXnrSl/EnG9taryrSuv/RDYSXpcK4GruIEY6/n9cZQnF0/CwLKh2DK2zGGCQ?= =?us-ascii?Q?x3VEzhp89rVOY+qCmzzuwSEP+yntFrI6r2dzbxRa7uGUlaSN4qNKcoSFzT8d?= =?us-ascii?Q?P/DLfnwzLM++yhwUpomB/Ed1Mo3XcLdzrA5eMHKj0LnKO5lQWUZIT8BAWt7T?= =?us-ascii?Q?Wucpe3mD4OGd3hglvQbYdMEP/4FQSgx/2WQJFWgi7/1LeW/+DXzj35DUoBc/?= =?us-ascii?Q?IAVjKLT3cuqiMgKi8X8hzxckpkD/WzLdIHcAa7D4XcAjQevjR/bSCma8BJRo?= =?us-ascii?Q?7SClcfdz694+aM/cbJViQ4TgMo4fD1KFQqFN2FDG/33faXmqpjVd1WHm5TC9?= =?us-ascii?Q?k+MjFnJ1cZQjJgLKlgjPJMIjRRh7QSzPxyfJGxaJdkBrsfN9SVr1fzOFEU7W?= =?us-ascii?Q?NcmXdcI94Es2hscfD/ptlV58zzYODSVYoVFv8NPEJGuWtSK9WR5XjUI8Wedh?= =?us-ascii?Q?4l2+EC+xAONNCj93wBZotJPVaIGW5WTYDPgLOPQsfav/WxqdZK2o8xGdw2QQ?= =?us-ascii?Q?BfDQk+DmP1i/XKfsgVccsQrIxejYqKJn0Ih5UVy920rPObbx39Ik1iggm3Wt?= =?us-ascii?Q?9OfmhwNMmdm/1ZnB8FMliOBJbAQNfn61hONGeL6W7CgGyaIFnDqDeNHy7N86?= =?us-ascii?Q?VLRmyMMl4F5w9TWYu1B/6oUzdYXdFomDpsHusaUcWGhcJNnjOep4eEHz+3Aa?= =?us-ascii?Q?R/j9FZ9TDfOktcp2IyEkoh1xOfVdfSr8fkmep37LWdlMFprihnL76g2BzB8A?= =?us-ascii?Q?sggPXdemd7ZN7jLjoYTSf3zoG9f7DKh6cFV?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2891; 6:7yrHsV9dn2VxLnxISBJ/iu5ioKZnP2rEnsf+S+z/GtUgKIVlR/hIbC9nwUQxcIOzxsc5mBABbni+JcylPfxQO/dL00pCro3vk701iCzaJ2bdnDNCw0XPy/xk6elGHJPjQ3PG2ZRG3RL7wgnciSvV0FZLc6ZUIZXmqWYnRnu+Q6TNrn3XfE2UR9bXerkbjHp+jnJ2j4Ei20pvN5gh23r5oyPstqFv+5dGzAwrm0kYlMbOPzR0jnqPK7GQwrN71y3uxsaQzJA5/SOo8yxMZxFoFOj3ssy4bzP/Upl7VjUOm9ngEDNXHKUG0TZFABe34ASD; 5:HgPCb8iF+isdKH2Zt1dR4997Dg7J4CJN4CEdVj/xyH7x/ZpbebimB29iQy/f502ghVmW5X3qYNgjknHsafr+S+M9d6prfFFgZqjwHr/Bu/1sAI0QD/FjuQ0nK++lJ3t+HOehwUbulPjPbi/HgdjtB8L66Z7ttu28hqZX8jUfFuBsriwZdvUQWeE0e5of/8cV; 24:jIPGpV61qnmbd1c+GWBACSOhB9hip8SxxWpyk1+Fgwf6KhDk4/rlu3ORqi8WBX2w3CJJDUVQPQZoG2LZjGBSpSQm98WiRwzn3if28RzjVAM= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2891; 7:g9qeO6fTb3wVRWXtGCT6WRysFxaXTY9HPgcvuU01kHS7z8xge017MOKTdnz0nziVYagRq1BV+LCGhahJ+Ezyj1wH3x61HzCYLaUaiHQRbzgI7K38h17SoGOnYK9Vka61ELE6/+h1w+m00m6anSnkMZGW5XUyxCcv5BADUwU/JSe0P46F4FK5UGLd5/JOQz3Bo+fm+MkC3YzJHU2BKVamPUG1Eoldu5VMEi9sqhfWA9YiravkpV0TQCRRA5ZnRKyVywD79A/Ku6KKDamtQu3gYTLB13x1D+VAIgvqM0rtIROC1q9F91fe1hHklymufMrQh6mY0EAChG2eJxr/7i7DzR3WbCulA7rQ4WsyquCD0w4= X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2016 05:57:04.4025 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2891 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161107_215732_516350_750787E4 X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Peng Fan , Bai Ping , Peter Chen , robh+dt@kernel.org, kernel@pengutronix.de, fabio.estevam@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bai Ping imx6ull is the derived SoC from imx6ul Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Peng Fan Signed-off-by: Bai Ping Signed-off-by: Peter Chen --- drivers/clk/imx/clk-imx6ul.c | 72 +++++++++++++++++++++++++++----- include/dt-bindings/clock/imx6ul-clock.h | 15 ++++++- 2 files changed, 75 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index d1d7787..75c35fb 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -64,6 +64,10 @@ static const char *perclk_sels[] = { "ipg", "osc", }; static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */ +static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; +static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; static struct clk *clks[IMX6UL_CLK_END]; static struct clk_onecell_data clk_data; @@ -102,6 +106,17 @@ static u32 share_count_audio; static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_esai; + +static inline int clk_on_imx6ul(void) +{ + return of_machine_is_compatible("fsl,imx6ul"); +} + +static inline int clk_on_imx6ull(void) +{ + return of_machine_is_compatible("fsl,imx6ull"); +} static void __init imx6ul_clocks_init(struct device_node *ccm_node) { @@ -238,12 +253,19 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); + if (clk_on_imx6ull()) + clks[IMX6ULL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels)); clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); - clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); - clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); + clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); + clks[IMX6ULL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); + } clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); @@ -276,6 +298,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); + if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); + clks[IMX6ULL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); + } clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); @@ -298,9 +324,15 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); - clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); - clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); - clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_DCP_CLK] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x68, 12); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x68, 12); + } clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); @@ -309,7 +341,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26); clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); - clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + if (clk_on_imx6ul()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + else if (clk_on_imx6ull()) + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18); /* CCGR1 */ clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -328,6 +363,11 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); /* CCGR2 */ + if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x70, 0, &share_count_esai); + clks[IMX6ULL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x70, 0, &share_count_esai); + clks[IMX6ULL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x70, 0, &share_count_esai); + } clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); @@ -340,8 +380,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) /* CCGR3 */ clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); - clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); - clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + } else if (clk_on_imx6ull()) { + clks[IMX6ULL_CLK_EPDC_ACLK] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4); + clks[IMX6ULL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); + } clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); @@ -385,8 +430,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); - clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + if (clk_on_imx6ul()) { + clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); + clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + } clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); @@ -441,7 +488,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) } clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]); - clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + if (clk_on_imx6ul()) + clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + else if (clk_on_imx6ull()) + clk_set_parent(clks[IMX6ULL_CLK_EPDC_PRE_SEL], clks[IMX6UL_CLK_PLL3_PFD2]); clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); } diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index fd8aee8..ee9f1a5 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -236,6 +236,19 @@ #define IMX6UL_CLK_PLL3_120M 223 #define IMX6UL_CLK_KPP 224 -#define IMX6UL_CLK_END 225 +/* For i.MX6ULL */ +#define IMX6ULL_CLK_ESAI_PRED 225 +#define IMX6ULL_CLK_ESAI_PODF 226 +#define IMX6ULL_CLK_ESAI_EXTAL 227 +#define IMX6ULL_CLK_ESAI_MEM 228 +#define IMX6ULL_CLK_ESAI_IPG 229 +#define IMX6ULL_CLK_DCP_CLK 230 +#define IMX6ULL_CLK_EPDC_PRE_SEL 231 +#define IMX6ULL_CLK_EPDC_SEL 232 +#define IMX6ULL_CLK_EPDC_PODF 233 +#define IMX6ULL_CLK_EPDC_ACLK 234 +#define IMX6ULL_CLK_EPDC_PIX 235 +#define IMX6ULL_CLK_ESAI_SEL 236 +#define IMX6UL_CLK_END 237 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */