From patchwork Wed Nov 9 22:58:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 9420309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B5AB7601C2 for ; Wed, 9 Nov 2016 23:03:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A68B229103 for ; Wed, 9 Nov 2016 23:03:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9B52429303; Wed, 9 Nov 2016 23:03:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 086FB29103 for ; Wed, 9 Nov 2016 23:03:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c4bs2-0003Wd-Rp; Wed, 09 Nov 2016 23:01:30 +0000 Received: from quartz.orcorp.ca ([184.70.90.242]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c4bpu-00013b-SU for linux-arm-kernel@lists.infradead.org; Wed, 09 Nov 2016 22:59:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=obsidianresearch.com; s=rsa1; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=PUhQ993AwCNN6nN0fvqgHFew2Q7v1ti9jOlhOhvOE5Q=; b=TzVsqfULYJiLJk/FQ3WhuAG3vz8VFZJkaYpFMaIZaSyYJsknZMDVL3DCfyt4PUUNmO1M2qcpNwQpoOLJA+R5ZDS+Dp2vF0HymqksKzi8nhzjx57BjhzrVmwoUnbRUXId078yOCB/zlhuFSJjrhSZznD+Xx72c6V0MPlQgx4Frn4=; Received: from [10.0.0.151] (helo=jggl.edm.orcorp.ca) by quartz.orcorp.ca with esmtps (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1c4bpG-00011i-JE; Wed, 09 Nov 2016 15:58:38 -0700 From: Jason Gunthorpe To: Alan Tull , Moritz Fischer Subject: [PATCH fpga 8/9] fpga socfpga: Use the scatterlist interface Date: Wed, 9 Nov 2016 15:58:22 -0700 Message-Id: <1478732303-13718-9-git-send-email-jgunthorpe@obsidianresearch.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1478732303-13718-1-git-send-email-jgunthorpe@obsidianresearch.com> References: <1478732303-13718-1-git-send-email-jgunthorpe@obsidianresearch.com> X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.151 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161109_145919_222041_F220EAF8 X-CRM114-Status: GOOD ( 14.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mike Looijmans , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Matthias Brugger , Michal Simek , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP socfpga just uses the CPU to memory copy the bitstream, so there is no reason it needs contiguous kernel memory. Switch to use the sg interface. Signed-off-by: Jason Gunthorpe --- drivers/fpga/socfpga.c | 56 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 27d2ff28132c..f3f390b2eecf 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Register offsets */ #define SOCFPGA_FPGMGR_STAT_OFST 0x0 @@ -408,10 +409,22 @@ static int socfpga_fpga_reset(struct fpga_manager *mgr) * Prepare the FPGA to receive the configuration data. */ static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, u32 flags, - const char *buf, size_t count) + struct sg_table *sgt) { struct socfpga_fpga_priv *priv = mgr->priv; - int ret; + struct scatterlist *sg; + int ret, i; + + /* We use the CPU to read the bitstream 32 bits at a time, and thus + * require alignment. + */ + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + if ((sg->offset % 4) != 0) { + dev_err(&mgr->dev, + "Invalid bitstream, chunks must be aligned\n"); + return -EINVAL; + } + } if (flags & FPGA_MGR_PARTIAL_RECONFIG) { dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); @@ -440,40 +453,45 @@ static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, u32 flags, /* * Step 9: write data to the FPGA data register */ -static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr, - const char *buf, size_t count) +static void socfpga_write_buf(struct socfpga_fpga_priv *priv, const u32 *buf, + size_t count) { - struct socfpga_fpga_priv *priv = mgr->priv; - u32 *buffer_32 = (u32 *)buf; size_t i = 0; - if (count <= 0) - return -EINVAL; - /* Write out the complete 32-bit chunks. */ while (count >= sizeof(u32)) { - socfpga_fpga_data_writel(priv, buffer_32[i++]); + socfpga_fpga_data_writel(priv, buf[i++]); count -= sizeof(u32); } /* Write out remaining non 32-bit chunks. */ switch (count) { case 3: - socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff); + socfpga_fpga_data_writel(priv, buf[i++] & 0x00ffffff); break; case 2: - socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff); + socfpga_fpga_data_writel(priv, buf[i++] & 0x0000ffff); break; case 1: - socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff); - break; - case 0: + socfpga_fpga_data_writel(priv, buf[i++] & 0x000000ff); break; default: - /* This will never happen. */ - return -EFAULT; + break; } +} + +static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr, + struct sg_table *sgt) +{ + struct socfpga_fpga_priv *priv = mgr->priv; + struct sg_mapping_iter miter; + + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + + while (sg_miter_next(&miter)) + socfpga_write_buf(priv, miter.addr, miter.length); + sg_miter_stop(&miter); return 0; } @@ -545,8 +563,8 @@ static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr) static const struct fpga_manager_ops socfpga_fpga_ops = { .state = socfpga_fpga_ops_state, - .write_init = socfpga_fpga_ops_configure_init, - .write = socfpga_fpga_ops_configure_write, + .write_init_sg = socfpga_fpga_ops_configure_init, + .write_sg = socfpga_fpga_ops_configure_write, .write_complete = socfpga_fpga_ops_configure_complete, };