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[v2,2/3] devicetree: bindings: nvmem: Add compatible string for imx6ul

Message ID 1479344899-3141-2-git-send-email-ping.bai@nxp.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jacky Bai Nov. 17, 2016, 1:08 a.m. UTC 
Add new compatible string for i.MX6UL SOC.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
Changes for V2:
- reformat the changes suggested by Rob Herring

 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Rob Herring (Arm) Nov. 18, 2016, 2:17 p.m. UTC | #1 
On Thu, Nov 17, 2016 at 09:08:18AM +0800, Bai Ping wrote:
> Add new compatible string for i.MX6UL SOC.
> 
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
> ---
> Changes for V2:
> - reformat the changes suggested by Rob Herring
> 
>  Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 383d588..966a72e 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,15 @@ 
 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
 
 This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
 
 Required properties:
 - compatible: should be one of
 	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
 	"fsl,imx6sl-ocotp" (i.MX6SL), or
-	"fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+	"fsl,imx6sx-ocotp" (i.MX6SX),
+	"fsl,imx6ul-ocotp" (i.MX6UL),
+	followed by "syscon".
 - reg: Should contain the register base and length.
 - clocks: Should contain a phandle pointing to the gated peripheral clock.