From patchwork Mon Nov 28 16:43:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jintack Lim X-Patchwork-Id: 9449763 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E696B600CB for ; Mon, 28 Nov 2016 16:47:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D758427EE9 for ; Mon, 28 Nov 2016 16:47:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C9F1727F46; Mon, 28 Nov 2016 16:47:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49A8027BFF for ; Mon, 28 Nov 2016 16:47:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cBP3V-0003tM-UK; Mon, 28 Nov 2016 16:45:25 +0000 Received: from outprodmail02.cc.columbia.edu ([128.59.72.51]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cBP3R-0002sK-CW for linux-arm-kernel@lists.infradead.org; Mon, 28 Nov 2016 16:45:22 +0000 Received: from hazelnut (hazelnut.cc.columbia.edu [128.59.213.250]) by outprodmail02.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id uASGe4c0050094 for ; Mon, 28 Nov 2016 11:44:58 -0500 Received: from hazelnut (localhost.localdomain [127.0.0.1]) by hazelnut (Postfix) with ESMTP id C2E1280 for ; Mon, 28 Nov 2016 11:44:58 -0500 (EST) Received: from sendprodmail03.cc.columbia.edu (sendprodmail03.cc.columbia.edu [128.59.72.15]) by hazelnut (Postfix) with ESMTP id 630EB8B for ; Mon, 28 Nov 2016 11:44:58 -0500 (EST) Received: from mail-qk0-f198.google.com (mail-qk0-f198.google.com [209.85.220.198]) by sendprodmail03.cc.columbia.edu (8.14.4/8.14.4) with ESMTP id uASGiwLO019332 (version=TLSv1/SSLv3 cipher=AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 28 Nov 2016 11:44:58 -0500 Received: by mail-qk0-f198.google.com with SMTP id x190so114612930qkb.5 for ; Mon, 28 Nov 2016 08:44:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HAKnOFkY+tUUIXCv7iFlBqgvaT0CR+2L6fM15Q2+SIg=; b=c2tJKvREnm022cMSf5mqCDuDBIfGTnnobZ2FyiDyiNOHi2+2QEGzyAo1rfz3s6N2HX oIpL60ySUnS0/3uknvOYGZEYgHYmAKPiOO33HLLAFLRlibq8dhjNY3RmuSNWGb4/M40e 4rlO8xGTn8SIlu2WmG25ompP8FiCgFT/ClbFV22TTqd0FM3+VIiY6kwVPvtF+LNbB5UL US3gQOCdqO81+pzdyuR9wIW9S1JCav77jh7aX//gqq13wnuxjjGzcb83W3gYxVPz4FSq wGyFcKTdQOsIUIGof2h73W1se/3ORsx3sjDvOb+EaMBzomTcI+FzEMowPJCX2bEhv3/k R1Mg== X-Gm-Message-State: AKaTC017rAuHCbKVSlP5Ka8KvT4ZDzriEozzaRemHvO8LvQzjofk/EuJqHD/hLvIIb/Zk11igsqaNeBEfQNjJHMKb/KT0B2fr1dnF0G5W0TK8w8QRdNVxrJD1PSuTpXzzxjWchtHaftYx7mk94YRBgQfyfwFhpq4VWyhNw== X-Received: by 10.55.15.95 with SMTP id z92mr19067093qkg.273.1480351497695; Mon, 28 Nov 2016 08:44:57 -0800 (PST) X-Received: by 10.55.15.95 with SMTP id z92mr19067065qkg.273.1480351497510; Mon, 28 Nov 2016 08:44:57 -0800 (PST) Received: from jintack.cs.columbia.edu ([2001:18d8:ffff:16:21a:4aff:feaa:f900]) by smtp.gmail.com with ESMTPSA id 21sm10369242qkh.4.2016.11.28.08.44.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Nov 2016 08:44:56 -0800 (PST) From: Jintack Lim To: kvmarm@lists.cs.columbia.edu Subject: [PATCH] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system Date: Mon, 28 Nov 2016 11:43:58 -0500 Message-Id: <1480351438-11548-1-git-send-email-jintack@cs.columbia.edu> X-Mailer: git-send-email 1.9.1 X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.78 on 128.59.72.15 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161128_084521_702981_69D2B792 X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, rkrcmar@redhat.com, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, julien.grall@arm.com, linux-arm-kernel@lists.infradead.org, andre.przywara@arm.com, pbonzini@redhat.com, Jintack , christoffer.dall@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jintack Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set. Current code is unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set. In fact, we don't need to set those two bits, which allow EL1 and EL0 to access physical timer and counter respectively, if E2H and TGE are set for the host kernel. They will be configured later as necessary. First, we don't need to configure those bits for EL1, since the host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process. Signed-off-by: Jintack Lim Acked-by: Marc Zyngier --- arch/arm64/kernel/head.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 332e331..bc3d2db 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -524,10 +524,16 @@ set_hcr: msr hcr_el2, x0 isb - /* Generic timers. */ + /* + * Allow Non-secure EL1 and EL0 to access physical timer and counter. + * This is not necessary for VHE, since the host kernel runs in EL2, + * and EL0 accesses are configured in the later stage of boot process. + */ + cbnz x2, 1f mrs x0, cnthctl_el2 orr x0, x0, #3 // Enable EL1 physical timers msr cnthctl_el2, x0 +1: msr cntvoff_el2, xzr // Clear virtual offset #ifdef CONFIG_ARM_GIC_V3