From patchwork Tue Dec 6 12:38:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 9462503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B0C726074E for ; Tue, 6 Dec 2016 12:46:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A29B427CAF for ; Tue, 6 Dec 2016 12:46:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9708B2838C; Tue, 6 Dec 2016 12:46:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9A18627CAF for ; Tue, 6 Dec 2016 12:46:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEF6h-000699-13; Tue, 06 Dec 2016 12:44:27 +0000 Received: from mail-wj0-x232.google.com ([2a00:1450:400c:c01::232]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEF2e-0001YU-Vj for linux-arm-kernel@lists.infradead.org; Tue, 06 Dec 2016 12:40:24 +0000 Received: by mail-wj0-x232.google.com with SMTP id v7so319036471wjy.2 for ; Tue, 06 Dec 2016 04:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S8Pmf0UrB3p46CvuJi9SH9oKcwGssjvWeqQ+KJXUqlI=; b=c5QbAfOIt7NH0oGl+nj2T0N6H5HqD2JOuY+hqH3dG2CEueYnkBJ8kp/GAGUKpLO47S 2Y/TzmHUTSGLQQt06ZMx7pJ66JRwVLP+D0Lq9k8HpEGwhmGzjzThgBGome9JmsmgQwuZ 8dN0vZTsNpMzTd11c5rUL8IXKbxLdA5ESTung= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S8Pmf0UrB3p46CvuJi9SH9oKcwGssjvWeqQ+KJXUqlI=; b=cEYmF3utB/kst2b/gPUXT9DZfs23iXotQ3cwox9O85zinDHY6s8PgPJkK8i46ABqXN Tr8sc3HkA3t8zUWEJbhVyn79K36W+gvHMJQ8MKHr/60O/RcyhlzJ7ye1JDXLENBY50kr aNZjARBIpLRLUjOeuUp+odDPMlo3Js/nSwRbpag6sMULjFKrX/8tf3T76iPNYNbXS44O b934x46BYzGleAltTNwWc9xR750yzgRmO081TuPN0pzsNsgoWDLK6jdt8kszC5Kzw0Ru F3ojDvX3OwbszhCcqF3CGq8Z6w1VN/4AOWk344apWCybiS3aP94I/IyOsch1HbY7To6M mVkg== X-Gm-Message-State: AKaTC01+A0jnPVJpYb7Yero6saa8jcBDgeFalVZG+Nk0DyPduWYEkbgKH6xK/xJgdKz0DtlI X-Received: by 10.194.101.97 with SMTP id ff1mr31282215wjb.67.1481027995144; Tue, 06 Dec 2016 04:39:55 -0800 (PST) Received: from lmenx321.st.com. ([80.215.93.98]) by smtp.gmail.com with ESMTPSA id k2sm25598089wjv.11.2016.12.06.04.39.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Dec 2016 04:39:54 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/7] PWM: add PWM driver for STM32 plaftorm Date: Tue, 6 Dec 2016 13:38:46 +0100 Message-Id: <1481027929-13704-5-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481027929-13704-1-git-send-email-benjamin.gaignard@st.com> References: <1481027929-13704-1-git-send-email-benjamin.gaignard@st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161206_044017_550285_4D303782 X-CRM114-Status: GOOD ( 24.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linaro-kernel@lists.linaro.org, Benjamin Gaignard , linus.walleij@linaro.org, arnaud.pouliquen@st.com, benjamin.gaignard@linaro.org, gerald.baeza@st.com, fabrice.gasnier@st.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This driver adds support for PWM driver on STM32 platform. The SoC have multiple instances of the hardware IP and each of them could have small differences: number of channels, complementary output, auto reload register size... version 4: - detect at probe time hardware capabilities - fix comments done on v2 and v3 - use PWM atomic ops version 2: - only keep one comptatible - use DT parameters to discover hardware block configuration Signed-off-by: Benjamin Gaignard --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-stm32.c | 363 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 375 insertions(+) create mode 100644 drivers/pwm/pwm-stm32.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index bf01288..95c9f04 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -388,6 +388,17 @@ config PWM_STI To compile this driver as a module, choose M here: the module will be called pwm-sti. +config PWM_STM32 + bool "STMicroelectronics STM32 PWM" + depends on ARCH_STM32 || COMPILE_TEST + depends on OF + depends on MFD_STM32_GP_TIMER + help + Generic PWM framework driver for STM32 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-stm32. + config PWM_STMPE bool "STMPE expander PWM export" depends on MFD_STMPE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 1194c54..5aa9308 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_STI) += pwm-sti.o +obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c new file mode 100644 index 0000000..319fd77 --- /dev/null +++ b/drivers/pwm/pwm-stm32.c @@ -0,0 +1,363 @@ +/* + * Copyright (C) STMicroelectronics 2016 + * + * Author: Gerald Baeza + * License terms: GNU General Public License (GPL), version 2 + * + * Inspired by timer-stm32.c from Maxime Coquelin + * pwm-atmel.c from Bo Shen + */ + +#include +#include +#include +#include + +#include + +#define CCMR_CHANNEL_SHIFT 8 +#define CCMR_CHANNEL_MASK 0xFF + +struct stm32_pwm { + struct pwm_chip chip; + struct device *dev; + struct clk *clk; + struct regmap *regmap; + unsigned int caps; + unsigned int npwm; + u32 breakinput_polarity; + u32 max_arr; + bool have_complementary_output; + bool have_breakinput; + bool use_breakinput; +}; + +#define to_stm32_pwm_dev(x) container_of(chip, struct stm32_pwm, chip) + +static u32 active_channels(struct stm32_pwm *dev) +{ + u32 ccer; + + regmap_read(dev->regmap, TIM_CCER, &ccer); + + return ccer & TIM_CCER_CCXE; +} + +static int write_ccrx(struct stm32_pwm *dev, struct pwm_device *pwm, + u32 value) +{ + switch (pwm->hwpwm) { + case 0: + return regmap_write(dev->regmap, TIM_CCR1, value); + case 1: + return regmap_write(dev->regmap, TIM_CCR2, value); + case 2: + return regmap_write(dev->regmap, TIM_CCR3, value); + case 3: + return regmap_write(dev->regmap, TIM_CCR4, value); + } + return -EINVAL; +} + +static int stm32_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + unsigned long long prd, div, dty; + unsigned int prescaler = 0; + u32 ccmr, mask, shift, bdtr; + + /* Period and prescaler values depends on clock rate */ + div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; + + do_div(div, NSEC_PER_SEC); + prd = div; + + while (div > priv->max_arr) { + prescaler++; + div = prd; + do_div(div, (prescaler + 1)); + } + + prd = div; + + if (prescaler > MAX_TIM_PSC) { + dev_err(chip->dev, "prescaler exceeds the maximum value\n"); + return -EINVAL; + } + + /* + * All channels share the same prescaler and counter so when two + * channels are active at the same we can't change them + */ + if (active_channels(priv) & ~(1 << pwm->hwpwm * 4)) { + u32 psc, arr; + + regmap_read(priv->regmap, TIM_PSC, &psc); + regmap_read(priv->regmap, TIM_ARR, &arr); + + if ((psc != prescaler) || (arr != prd - 1)) + return -EBUSY; + } + + regmap_write(priv->regmap, TIM_PSC, prescaler); + regmap_write(priv->regmap, TIM_ARR, prd - 1); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); + + /* Calculate the duty cycles */ + dty = prd * duty_ns; + do_div(dty, period_ns); + + write_ccrx(priv, pwm, dty); + + /* Configure output mode */ + shift = (pwm->hwpwm & 0x1) * CCMR_CHANNEL_SHIFT; + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; + mask = CCMR_CHANNEL_MASK << shift; + + if (pwm->hwpwm < 2) + regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); + else + regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); + + if (!priv->have_breakinput) + return 0; + + bdtr = TIM_BDTR_MOE | TIM_BDTR_AOE; + + if (priv->use_breakinput) + bdtr |= TIM_BDTR_BKE; + + if (priv->breakinput_polarity) + bdtr |= TIM_BDTR_BKP; + + regmap_update_bits(priv->regmap, TIM_BDTR, + TIM_BDTR_MOE | TIM_BDTR_AOE | + TIM_BDTR_BKP | TIM_BDTR_BKE, + bdtr); + + return 0; +} + +static int stm32_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + u32 mask; + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + + mask = TIM_CCER_CC1P << (pwm->hwpwm * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NP << (pwm->hwpwm * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, + polarity == PWM_POLARITY_NORMAL ? 0 : mask); + + return 0; +} + +static int stm32_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 mask; + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + + clk_enable(priv->clk); + + /* Enable channel */ + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); + + /* Make sure that registers are updated */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + + /* Enable controller */ + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + + return 0; +} + +static void stm32_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 mask; + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + + /* Disable channel */ + mask = TIM_CCER_CC1E << (pwm->hwpwm * 4); + if (priv->have_complementary_output) + mask |= TIM_CCER_CC1NE << (pwm->hwpwm * 4); + + regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); + + /* When all channels are disabled, we can disable the controller */ + if (!active_channels(priv)) + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + + clk_disable(priv->clk); +} + +static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pwm_state curstate; + bool enabled; + int ret; + + pwm_get_state(pwm, &curstate); + enabled = curstate.enabled; + + if (enabled && !state->enabled) { + stm32_pwm_disable(chip, pwm); + return 0; + } + + if (state->polarity != curstate.polarity && enabled) + stm32_pwm_set_polarity(chip, pwm, state->polarity); + + ret = stm32_pwm_config(chip, pwm, state->duty_cycle, state->period); + if (ret) + return ret; + + if (!enabled && state->enabled) + ret = stm32_pwm_enable(chip, pwm); + + return ret; +} + +static const struct pwm_ops stm32pwm_ops = { + .owner = THIS_MODULE, + .apply = stm32_pwm_apply, +}; + +static bool stm32_pwm_detect_breakinput(struct regmap *regmap) +{ + u32 bdtr; + + /* + * If breakinput enable bit doesn't exist writing 1 will have no + * effect so we can detect it. + */ + regmap_update_bits(regmap, TIM_BDTR, TIM_BDTR_BKE, TIM_BDTR_BKE); + regmap_read(regmap, TIM_BDTR, &bdtr); + regmap_update_bits(regmap, TIM_BDTR, TIM_BDTR_BKE, 0); + + return (bdtr != 0); +} + +static bool stm32_pwm_detect_complementary(struct regmap *regmap) +{ + u32 ccer; + + /* + * If complementary bit doesn't exist writing 1 will have no + * effect so we can detect it. + */ + regmap_update_bits(regmap, TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE); + regmap_read(regmap, TIM_CCER, &ccer); + regmap_update_bits(regmap, TIM_CCER, TIM_CCER_CCXE, 0); + + return (ccer != 0); +} + +static int stm32_pwm_detect_channels(struct regmap *regmap) +{ + int channels = 0; + u32 ccer; + + /* + * If channels enable bits don't exist writing 1 will have no + * effect so we can detect and count them. + */ + regmap_update_bits(regmap, TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE); + regmap_read(regmap, TIM_CCER, &ccer); + regmap_update_bits(regmap, TIM_CCER, TIM_CCER_CCXE, 0); + + if (ccer & TIM_CCER_CC1E) + channels++; + + if (ccer & TIM_CCER_CC2E) + channels++; + + if (ccer & TIM_CCER_CC3E) + channels++; + + if (ccer & TIM_CCER_CC4E) + channels++; + + return channels; +} + +static int stm32_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct stm32_gptimer *ddata = dev_get_drvdata(pdev->dev.parent); + struct stm32_pwm *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = ddata->regmap; + priv->clk = ddata->clk; + priv->max_arr = ddata->max_arr; + + if (!priv->regmap || !priv->clk) + return -EINVAL; + + priv->have_breakinput = stm32_pwm_detect_breakinput(priv->regmap); + priv->have_complementary_output = + stm32_pwm_detect_complementary(priv->regmap); + priv->npwm = stm32_pwm_detect_channels(priv->regmap); + + if (!of_property_read_u32(np, "st,breakinput-polarity", + &priv->breakinput_polarity)) + priv->use_breakinput = true; + + priv->chip.base = -1; + priv->chip.dev = dev; + priv->chip.ops = &stm32pwm_ops; + priv->chip.npwm = priv->npwm; + + ret = pwmchip_add(&priv->chip); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int stm32_pwm_remove(struct platform_device *pdev) +{ + struct stm32_pwm *priv = platform_get_drvdata(pdev); + unsigned int i; + + for (i = 0; i < priv->npwm; i++) + pwm_disable(&priv->chip.pwms[i]); + + pwmchip_remove(&priv->chip); + + return 0; +} + +static const struct of_device_id stm32_pwm_of_match[] = { + { .compatible = "st,stm32-pwm", } +}; +MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); + +static struct platform_driver stm32_pwm_driver = { + .probe = stm32_pwm_probe, + .remove = stm32_pwm_remove, + .driver = { + .name = "stm32-pwm", + .of_match_table = stm32_pwm_of_match, + }, +}; +module_platform_driver(stm32_pwm_driver); + +MODULE_ALIAS("platform: stm32-pwm"); +MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); +MODULE_LICENSE("GPL v2");