@@ -90,7 +90,7 @@
};
uart0: serial@02530c00 {
- compatible = "ns16550a";
+ compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -35,7 +35,7 @@
/include/ "keystone-k2l-clocks.dtsi"
uart2: serial@02348400 {
- compatible = "ns16550a";
+ compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -45,7 +45,7 @@
};
uart3: serial@02348800 {
- compatible = "ns16550a";
+ compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -98,7 +98,7 @@
/include/ "keystone-clocks.dtsi"
uart0: serial@02530c00 {
- compatible = "ns16550a";
+ compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -108,7 +108,7 @@
};
uart1: serial@02531000 {
- compatible = "ns16550a";
+ compatible = "ti,da830-uart", "ns16550a";
current-speed = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
The TI Keystone SoCs have extra UART registers beyond the standard 8250 registers, so we need a new compatible string to indicate this. Also, at least one of these registers uses the full 32 bits, so we need to specify reg-io-width in addition to reg-shift. "ns16550a" is left in the compatible specification since it does work as long as the bootloader configures the SoC UART power management registers. Signed-off-by: David Lechner <david@lechnology.com> --- v3 changes: * None v2 changes: * This is a new patch in v2 arch/arm/boot/dts/keystone-k2g.dtsi | 2 +- arch/arm/boot/dts/keystone-k2l.dtsi | 4 ++-- arch/arm/boot/dts/keystone.dtsi | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)