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Sun, 08 Jan 2017 22:26:05 -0800 (PST) Received: from jintack.cs.columbia.edu ([2001:18d8:ffff:16:21a:4aff:feaa:f900]) by smtp.gmail.com with ESMTPSA id h3sm8623257qtc.6.2017.01.08.22.26.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Jan 2017 22:26:04 -0800 (PST) From: Jintack Lim To: christoffer.dall@linaro.org, marc.zyngier@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, vladimir.murzin@arm.com, suzuki.poulose@arm.com, mark.rutland@arm.com, james.morse@arm.com, lorenzo.pieralisi@arm.com, kevin.brodsky@arm.com, wcohen@redhat.com, shankerd@codeaurora.org, geoff@infradead.org, andre.przywara@arm.com, eric.auger@redhat.com, anna-maria@linutronix.de, shihwei@cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC 26/55] KVM: arm/arm64: Add VGIC data structures for the nesting Date: Mon, 9 Jan 2017 01:24:22 -0500 Message-Id: <1483943091-1364-27-git-send-email-jintack@cs.columbia.edu> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483943091-1364-1-git-send-email-jintack@cs.columbia.edu> References: <1483943091-1364-1-git-send-email-jintack@cs.columbia.edu> X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.78 on 128.59.72.16 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170108_222627_089727_D6696158 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jintack@cs.columbia.edu MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Christoffer Dall This adds a couple of extra data structures: The nested_vgic_vX structures contain the data manipulated by the guest hypervisor when it faults/traps on accesses to the GICH_ interface. The shadow_vgic_vX arrays contain the shadow copies of the LRs. That is, it is a modified version of the nested_vgic_vX->vgic_lr. The reason why we need a modified version is that for interrupts with the HW bit set (those for the timer) the interrupt number must be that of the host hardware number, and not the virtual one programmed by the guest hypervisor. The hw_vX_cpu_if pointers point to the registers that the lowvisor (EL2) code actually copied into hardware when switching to the guest, so at init time we set: vgic_cpu->hw_v2_cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; And we should change the vgic-sr function to read the LRs from the hw_v2_lr pointer. Signed-off-by: Christoffer Dall Signed-off-by: Jintack Lim --- include/kvm/arm_vgic.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 002f092..9a9cb27 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -246,6 +246,26 @@ struct vgic_cpu { unsigned int used_lrs; struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; + /* CPU vif control registers for the virtual GICH interface */ + union { + struct vgic_v2_cpu_if nested_vgic_v2; + struct vgic_v3_cpu_if nested_vgic_v3; + }; + + /* + * The shadow vif control register loaded to the hardware when + * running a sted L2 guest with the virtual IMO bit set. + */ + union { + struct vgic_v2_cpu_if shadow_vgic_v2; + struct vgic_v3_cpu_if shadow_vgic_v3; + }; + + union { + struct vgic_v2_cpu_if *hw_v2_cpu_if; + struct vgic_v3_cpu_if *hw_v3_cpu_if; + }; + spinlock_t ap_list_lock; /* Protects the ap_list */ /*