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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v9sm1244425lja.0.2017.01.11.03.52.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Jan 2017 03:52:24 -0800 (PST) From: Tomasz Nowicki To: will.deacon@arm.com, robin.murphy@arm.com, mark.rutland@arm.com, joro@8bytes.org Subject: [PATCH 1/1] iommu/arm-smmu: Fix for ThunderX erratum #27704 Date: Wed, 11 Jan 2017 12:51:47 +0100 Message-Id: <1484135507-24872-1-git-send-email-tn@semihalf.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170111_065249_367497_1E2F037E X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Prasun.Kapoor@cavium.com, Sunil.Goutham@cavium.com, Tomasz Nowicki , linux-kernel@vger.kernel.org, Tirumalesh.Chalamarla@cavium.com, Geethasowjanya.Akula@cavium.com, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs are unique across all SMMU instances on affected Cavium systems. Currently, the workaround code partitions ASIDs and VMIDs by increasing global cavium_smmu_context_count which in turn becomes the base ASID and VMID value for the given SMMU instance upon the context bank initialization. For systems with multiple SMMU instances this approach implies the risk of crossing 8-bit ASID, like for CN88xx capable of 4 SMMUv2, 128 context bank each: SMMU_0 (0-127 ASID RANGE) SMMU_1 (127-255 ASID RANGE) SMMU_2 (256-383 ASID RANGE) <--- crossing 8-bit ASID SMMU_3 (384-511 ASID RANGE) <--- crossing 8-bit ASID Since we use 8-bit ASID now we effectively misconfigure ASID[15:8] bits for SMMU_CBn_TTBRm register. Also, we still use non-zero ASID[15:8] bits upon context invalidation. This patch adds 16-bit ASID support for stage-1 AArch64 contexts for Cavium SMMUv2 model so that we use ASIDs consistently. Signed-off-by: Tomasz Nowicki Reviewed-by: Robin Murphy --- drivers/iommu/arm-smmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index a60cded..ae8f059 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -260,6 +260,7 @@ enum arm_smmu_s2cr_privcfg { #define TTBCR2_SEP_SHIFT 15 #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) +#define TTBCR2_AS (1 << 4) #define TTBRn_ASID_SHIFT 48 @@ -778,6 +779,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; reg2 |= TTBCR2_SEP_UPSTREAM; + if (smmu->model == CAVIUM_SMMUV2 && + cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) + reg2 |= TTBCR2_AS; } if (smmu->version > ARM_SMMU_V1) writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);