| Message ID | 1484649143-19423-2-git-send-email-pankaj.dubey@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hello Pankaj, On 01/17/2017 07:32 AM, Pankaj Dubey wrote: > Add USB 3.0 DRD controller device node, with its clock > and phy information to enable the same on Exynos7. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com> The S-o-B order isn't correct. You are the one posting the patch so yours should be the last one. Also, wasn't this patch originally from Vivek? If you didn't change that much, I think that he should be listed as the patch author. I don't have an Exynos7 manual to verify but the patch looks good. Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Best regards,
Hi Javier, On Tuesday 17 January 2017 07:07 PM, Javier Martinez Canillas wrote: > Hello Pankaj, > > On 01/17/2017 07:32 AM, Pankaj Dubey wrote: >> Add USB 3.0 DRD controller device node, with its clock >> and phy information to enable the same on Exynos7. >> >> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> >> Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com> > > The S-o-B order isn't correct. You are the one posting the patch so > yours should be the last one. > > Also, wasn't this patch originally from Vivek? If you didn't change > that much, I think that he should be listed as the patch author. > Thanks for review. Just noticed, I missed to take care of this, as original patch could not be applied on latest tree and I had to do all these changes manually, will submit soon with Signed-off-by and author change. Thanks, Pankaj Dubey > I don't have an Exynos7 manual to verify but the patch looks good. > > Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> > > Best regards, >
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 9080a11..a2d8d11 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -603,6 +603,40 @@ #include "exynos7-trip-points.dtsi" }; }; + + usbdrd_phy: phy@15500000 { + compatible = "samsung,exynos7-usbdrd-phy"; + reg = <0x15500000 0x100>; + clocks = <&clock_fsys0 ACLK_USBDRD300>, + <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 SCLK_USBDRD300_REFCLK>; + clock-names = "phy", "ref", "phy_pipe", + "phy_utmi", "itp"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbdrd3: usb@15400000 { + compatible = "samsung,exynos7-dwusb3"; + clocks = <&clock_fsys0 ACLK_USBDRD300>, + <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, + <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; + clock-names = "usbdrd30", "usbdrd30_susp_clk", + "usbdrd30_axius_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x15400000 0x10000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; }; };