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Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR0301MB1581 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170118_144011_893681_689199D9 X-CRM114-Status: GOOD ( 10.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: roy.pledge@nxp.com Cc: Roy Pledge , madalin.bucur@nxp.com, scott.wood@nxp.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Rework ioremap() for PPC and ARM. The PPC devices require a non-coherent mapping while ARM will work with a non-cachable/write combine mapping. Signed-off-by: Roy Pledge --- drivers/soc/fsl/qbman/bman_portal.c | 16 +++++++++++++--- drivers/soc/fsl/qbman/qman_portal.c | 16 +++++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/soc/fsl/qbman/bman_portal.c b/drivers/soc/fsl/qbman/bman_portal.c index 8354d4d..a661f30 100644 --- a/drivers/soc/fsl/qbman/bman_portal.c +++ b/drivers/soc/fsl/qbman/bman_portal.c @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device *pdev) } pcfg->irq = irq; - va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0); +#ifdef CONFIG_PPC + /* PPC requires a cacheable/non-coherent mapping of the portal */ + va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), + (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT)); +#else + /* + * For ARM we can use write combine mapping. A cacheable/non shareable + * mapping will perform better but equires additional platform + * support which is not currently available + */ + va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0])); +#endif if (!va) { dev_err(dev, "ioremap::CE failed\n"); goto err_ioremap1; @@ -133,8 +144,7 @@ static int bman_portal_probe(struct platform_device *pdev) pcfg->addr_virt[DPAA_PORTAL_CE] = va; - va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]), - _PAGE_GUARDED | _PAGE_NO_CACHE); + va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1])); if (!va) { dev_err(dev, "ioremap::CI failed\n"); goto err_ioremap2; diff --git a/drivers/soc/fsl/qbman/qman_portal.c b/drivers/soc/fsl/qbman/qman_portal.c index adbaa30..e7a9eef 100644 --- a/drivers/soc/fsl/qbman/qman_portal.c +++ b/drivers/soc/fsl/qbman/qman_portal.c @@ -265,7 +265,18 @@ static int qman_portal_probe(struct platform_device *pdev) } pcfg->irq = irq; - va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0); +#ifdef CONFIG_PPC + /* PPC requires a cacheable/non-coherent mapping of the portal */ + va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), + (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT)); +#else + /* + * For ARM we can use write combine mapping. A cacheable/non shareable + * mapping will perform better but equires additional platform + * support which is not currently available + */ + va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0])); +#endif if (!va) { dev_err(dev, "ioremap::CE failed\n"); goto err_ioremap1; @@ -273,8 +284,7 @@ static int qman_portal_probe(struct platform_device *pdev) pcfg->addr_virt[DPAA_PORTAL_CE] = va; - va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]), - _PAGE_GUARDED | _PAGE_NO_CACHE); + va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1])); if (!va) { dev_err(dev, "ioremap::CI failed\n"); goto err_ioremap2;