From patchwork Fri Jan 20 09:15:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 9527793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A01EE6020B for ; Fri, 20 Jan 2017 09:18:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 93E1F28626 for ; Fri, 20 Jan 2017 09:18:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 884DA28683; Fri, 20 Jan 2017 09:18:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_SORBS_SPAM,T_DKIM_INVALID autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 409C328626 for ; Fri, 20 Jan 2017 09:18:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cUVKl-0004kL-KT; Fri, 20 Jan 2017 09:18:11 +0000 Received: from mail-wm0-f52.google.com ([74.125.82.52]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cUVKC-0003dy-AF for linux-arm-kernel@lists.infradead.org; Fri, 20 Jan 2017 09:17:39 +0000 Received: by mail-wm0-f52.google.com with SMTP id c206so33990268wme.0 for ; Fri, 20 Jan 2017 01:17:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uPZwztIgvwC0Gxel35zktwI1wkk6WfX2oGZSiTzR3fk=; b=gUHG68/NaAU/CMOa2hzKLZ0uX9ID8qNRLyR26Fivogt5kl81Mip+jDcUEFYZDATmKV w1nehaXVcLe7FgJb5Tzt2KKuDCc+ZSPWpOmJQOPuU8KE3eUjzVsBS2ojlJY8voqAueiy Xj/g3HS7ZNJUMz/Cq6j+Heqcz6q5W+y+VeNbc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uPZwztIgvwC0Gxel35zktwI1wkk6WfX2oGZSiTzR3fk=; b=M8Py8FYemD6HXoJ+fzgQvwLVmge90st5GT3Yx4hVTgBYZQLh8IlyDFHiAqwKkEPuES pjrr0NgtFcFpKGEZahphlkLe7tA+h0RauzpdmF7Nw2Bnc0w68mdG38Ry620FiiMV/Y5P szkPxw6OZqqVXmN1lw9K0TCcJAiyGo5aeCgs0o921iSmN9jB1vKRWQmBR8Chhf6XjESp dgxcwUXGn9lPbRKJECEXfKYfox1oUsBeFTuzlIadD7UVmyixce63EZV0NezVS+YKkOfm bwqDi4SC7GC6hgJQm2oVv2jUOvxVMtCDJFeyVHpfIHUAowhe7tuzq6TU5PVqiYZwEjpc G/0Q== X-Gm-Message-State: AIkVDXJx3ElZ172nPKVe8ppgPgr7NXmCBmgQmoK3HlBnkDcMGEFgeSDmZnKECUtfTUnCI0pQ X-Received: by 10.28.211.205 with SMTP id k196mr2325126wmg.124.1484903774537; Fri, 20 Jan 2017 01:16:14 -0800 (PST) Received: from lmenx321.st.com. ([80.215.47.82]) by smtp.gmail.com with ESMTPSA id r6sm4766132wmd.4.2017.01.20.01.16.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 01:16:14 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 1/8] MFD: add bindings for STM32 Timers driver Date: Fri, 20 Jan 2017 10:15:02 +0100 Message-Id: <1484903709-11650-2-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1484903709-11650-1-git-send-email-benjamin.gaignard@st.com> References: <1484903709-11650-1-git-send-email-benjamin.gaignard@st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170120_011736_648229_1369368B X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linaro-kernel@lists.linaro.org, Benjamin Gaignard , arnaud.pouliquen@st.com, benjamin.gaignard@linaro.org, gerald.baeza@st.com, fabrice.gasnier@st.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings information for STM32 Timers version 6: - rename stm32-gtimer to stm32-timers - change compatible - add description about the IPs version 2: - rename stm32-mfd-timer to stm32-gptimer - only keep one compatible string Signed-off-by: Benjamin Gaignard Acked-by: Lee Jones Acked-by: Rob Herring --- .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt new file mode 100644 index 0000000..bbd083f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -0,0 +1,46 @@ +STM32 Timers driver bindings + +This IP provides 3 types of timer along with PWM functionality: +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels. +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a + programmable prescaler and PWM outputs. +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. + +Required parameters: +- compatible: must be "st,stm32-timers" + +- reg: Physical base address and length of the controller's + registers. +- clock-names: Set to "int". +- clocks: Phandle to the clock used by the timer module. + For Clk properties, please refer to ../clock/clock-bindings.txt + +Optional parameters: +- resets: Phandle to the parent reset controller. + See ../reset/st,stm32-rcc.txt + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32.txt +- timer: See ../iio/timer/stm32-timer-trigger.txt + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + }; + };