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Thu, 26 Jan 2017 17:05:07 -0800 (PST) Received: from jintack.cs.columbia.edu ([2001:18d8:ffff:16:21a:4aff:feaa:f900]) by smtp.gmail.com with ESMTPSA id f68sm2709538qkf.34.2017.01.26.17.05.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jan 2017 17:05:07 -0800 (PST) From: Jintack Lim To: pbonzini@redhat.com, rkrcmar@redhat.com, christoffer.dall@linaro.org, marc.zyngier@arm.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, andre.przywara@arm.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Subject: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level Date: Thu, 26 Jan 2017 20:04:56 -0500 Message-Id: <1485479100-4966-7-git-send-email-jintack@cs.columbia.edu> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1485479100-4966-1-git-send-email-jintack@cs.columbia.edu> References: <1485479100-4966-1-git-send-email-jintack@cs.columbia.edu> X-No-Spam-Score: Local X-Scanned-By: MIMEDefang 2.78 on 128.59.72.15 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170126_170537_653269_1E8C25BB X-CRM114-Status: GOOD ( 12.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Note that the emulated EL1 physical timer is not mapped to any hardware timer, so we call a proper vgic function. Signed-off-by: Jintack Lim --- virt/kvm/arm/arch_timer.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 0f6e935..3b6bd50 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -180,6 +180,21 @@ static void kvm_timer_update_mapped_irq(struct kvm_vcpu *vcpu, bool new_level, WARN_ON(ret); } +static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, + struct arch_timer_context *timer) +{ + int ret; + + BUG_ON(!vgic_initialized(vcpu->kvm)); + + timer->irq.level = new_level; + trace_kvm_timer_update_irq(vcpu->vcpu_id, timer->irq.irq, + timer->irq.level); + ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, timer->irq.irq, + timer->irq.level); + WARN_ON(ret); +} + /* * Check if there was a change in the timer state (should we raise or lower * the line level to the GIC). @@ -188,6 +203,7 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu) { struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu; struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); + struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); /* * If userspace modified the timer registers via SET_ONE_REG before @@ -201,6 +217,10 @@ static int kvm_timer_update_state(struct kvm_vcpu *vcpu) if (kvm_timer_should_fire(vcpu, vtimer) != vtimer->irq.level) kvm_timer_update_mapped_irq(vcpu, !vtimer->irq.level, vtimer); + /* The emulated EL1 physical timer irq is not mapped to hardware */ + if (kvm_timer_should_fire(vcpu, ptimer) != ptimer->irq.level) + kvm_timer_update_irq(vcpu, !ptimer->irq.level, ptimer); + return 0; }