@@ -23,6 +23,11 @@ static void __init imx25_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX25);
}
+static void __init imx25_dt_init(void)
+{
+ imx_aips_allow_unprivileged_access("fsl,imx25-aips");
+}
+
static void __init mx25_init_irq(void)
{
struct device_node *np;
@@ -41,6 +46,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.init_early = imx25_init_early,
+ .init_machine = imx25_dt_init,
.init_late = imx25_pm_init,
.init_irq = mx25_init_irq,
.dt_compat = imx25_dt_board_compat,
The problem described in 6befda9a272b98bfb1dc772efc3564644cbfb270 for the i.MX53 platform applies to i.MX25 as well. E.g. CSPI1+SDMA and SSI1+SDMA are not working with the default AIPS configuration. Modifiy the AIPS configuration to allow access to the bus by SDMA and peripherals. Signed-off-by: Martin Kaiser <martin@kaiser.cx> --- arch/arm/mach-imx/mach-imx25.c | 6 ++++++ 1 file changed, 6 insertions(+)