From patchwork Wed Feb 15 21:50:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 9575163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2FA9B6045F for ; Wed, 15 Feb 2017 21:50:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F7DF28531 for ; Wed, 15 Feb 2017 21:50:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 118092855B; Wed, 15 Feb 2017 21:50:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 371B928544 for ; Wed, 15 Feb 2017 21:50:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=iaDH842B4dGEUxYddSyMHUaXXT+8EY2T9h7ZfW0jaZA=; b=XimBW9eTQrzKdf8DTWgAYA3hvC 6m90ri9vVT9KQ9xwKyKi7b6vD/DuctVkj12cwDPxb2wbt8/UzVrLtO/naJH/ajekq2jyAnt8cVEaP 86gFS+2aqXADFH7ORgsmWfZ5XBdcMDfM+oyUI4XBENoFeeNX/GxycgQeRDX4cXadM7miQDFdBBLxM uglVJsUIkBzfmFRNbm+8D6xFGnJ8tHNLidjT3wBohKo6GnSGS58VpJI2uK9ZDk9TG/So3DLWun6Wr CBuvHDRYmiKfI7P0l9UgrVzd1L3Al0lmtcwUy8rKsg1YOrLgfuudSw6jyOViGQ8lG6g9ly9bv/Q2P Y+RD6rgA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ce7Sv-0005yk-Dg; Wed, 15 Feb 2017 21:50:21 +0000 Received: from mga14.intel.com ([192.55.52.115]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ce7RF-0003Qj-K4 for linux-arm-kernel@lists.infradead.org; Wed, 15 Feb 2017 21:48:41 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Feb 2017 13:48:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,166,1484035200"; d="scan'208";a="45135114" Received: from tthayer-hp-z620-ubuntu.an.intel.com (HELO tthayer-HP-Z620-Ubuntu.altera.com) ([10.122.105.144]) by orsmga002.jf.intel.com with ESMTP; 15 Feb 2017 13:48:20 -0800 From: thor.thayer@linux.intel.com To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, linux@armlinux.org.uk, p.zabel@pengutronix.de Subject: [PATCH 3/5] reset: Add Altera Arria10 System Resource Reset Controller Date: Wed, 15 Feb 2017 15:50:14 -0600 Message-Id: <1487195416-23827-4-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487195416-23827-1-git-send-email-thor.thayer@linux.intel.com> References: <1487195416-23827-1-git-send-email-thor.thayer@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170215_134837_779172_11C8C1A4 X-CRM114-Status: GOOD ( 19.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, thor.thayer@linux.intel.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer This patch adds the reset controller functionality to the Arria10 System Resource Manager. Signed-off-by: Thor Thayer --- MAINTAINERS | 1 + drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-a10sr.c | 176 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 185 insertions(+) create mode 100644 drivers/reset/reset-a10sr.c diff --git a/MAINTAINERS b/MAINTAINERS index a2c74db..3265cb2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -655,6 +655,7 @@ F: drivers/gpio/gpio-altera-a10sr.c F: drivers/mfd/altera-a10sr.c F: include/linux/mfd/altera-a10sr.h F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h +F: drivers/reset/reset-a10sr.c ALTERA TRIPLE SPEED ETHERNET DRIVER M: Vince Bridgers diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index f4cdfe9..b821d1b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -39,6 +39,13 @@ config RESET_MESON help This enables the reset driver for Amlogic Meson SoCs. +config ALTERA_A10SR_RESET + tristate "Altera Arria10 System Resource Reset" + depends on MFD_ALTERA_A10SR + help + This option enables support for the external reset functions for + peripheral PHYs on the Altera Arria10 System Resource Chip. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2cd3f6c..d6a2a87 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o +obj-$(CONFIG_ALTERA_A10SR_RESET) += reset-a10sr.o diff --git a/drivers/reset/reset-a10sr.c b/drivers/reset/reset-a10sr.c new file mode 100644 index 0000000..ed058f3 --- /dev/null +++ b/drivers/reset/reset-a10sr.c @@ -0,0 +1,176 @@ +/* + * Copyright Intel Corporation (C) 2017. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * Reset driver for Altera Arria10 MAX5 System Resource Chip + * + * Adapted from reset-socfpga.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Number of A10 System Controller Resets */ +#define A10SR_RESETS 16 + +struct a10sr_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static inline struct a10sr_reset *to_a10sr_rst(struct reset_controller_dev *rc) +{ + return container_of(rc, struct a10sr_reset, rcdev); +} + +static inline int a10sr_reset_shift(unsigned long id) +{ + switch (id) { + case A10SR_RESET_ENET_HPS: + return 1; + case A10SR_RESET_PCIE: + case A10SR_RESET_FILE: + case A10SR_RESET_BQSPI: + case A10SR_RESET_USB: + return id + 11; + default: + return -EINVAL; + } +} + +static int a10sr_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct a10sr_reset *a10r = to_a10sr_rst(rcdev); + int offset = a10sr_reset_shift(id); + u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); + int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset); + + if (id >= rcdev->nr_resets) + return -EINVAL; + + return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); +} + +static int a10sr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return a10sr_reset_update(rcdev, id, true); +} + +static int a10sr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return a10sr_reset_update(rcdev, id, false); +} + +static int a10sr_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int error; + struct a10sr_reset *a10r = to_a10sr_rst(rcdev); + int offset = a10sr_reset_shift(id); + u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); + int index = ALTR_A10SR_HPS_RST_REG + ALTR_A10SR_REG_OFFSET(offset); + unsigned int value; + + if (id >= rcdev->nr_resets) + return -EINVAL; + + error = regmap_read(a10r->regmap, index, &value); + if (error < 0) + return -ENOMEM; + + return !!(value & mask); +} + +static const struct reset_control_ops a10sr_reset_ops = { + .assert = a10sr_reset_assert, + .deassert = a10sr_reset_deassert, + .status = a10sr_reset_status, +}; + +static const struct of_device_id a10sr_reset_of_match[]; +static int a10sr_reset_probe(struct platform_device *pdev) +{ + struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent); + struct a10sr_reset *a10r; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + + /* Ensure we have a valid DT entry. */ + np = of_find_matching_node(NULL, a10sr_reset_of_match); + if (!np) { + dev_err(&pdev->dev, "A10 Reset DT Entry not found\n"); + return -EINVAL; + } + + if (!of_find_property(np, "#reset-cells", NULL)) { + dev_err(&pdev->dev, "%s missing #reset-cells property\n", + np->full_name); + return -EINVAL; + } + + a10r = devm_kzalloc(&pdev->dev, sizeof(struct a10sr_reset), + GFP_KERNEL); + if (!a10r) + return -ENOMEM; + + a10r->rcdev.owner = THIS_MODULE; + a10r->rcdev.nr_resets = A10SR_RESETS; + a10r->rcdev.ops = &a10sr_reset_ops; + a10r->rcdev.of_node = np; + a10r->regmap = a10sr->regmap; + + platform_set_drvdata(pdev, a10r); + + return devm_reset_controller_register(dev, &a10r->rcdev); +} + +static int a10sr_reset_remove(struct platform_device *pdev) +{ + struct a10sr_reset *a10r = platform_get_drvdata(pdev); + + reset_controller_unregister(&a10r->rcdev); + + return 0; +} + +static const struct of_device_id a10sr_reset_of_match[] = { + { .compatible = "altr,a10sr-reset" }, + { }, +}; +MODULE_DEVICE_TABLE(of, a10sr_reset_of_match); + +static struct platform_driver a10sr_reset_driver = { + .probe = a10sr_reset_probe, + .remove = a10sr_reset_remove, + .driver = { + .name = "altr_a10sr_reset", + .owner = THIS_MODULE, + }, +}; +module_platform_driver(a10sr_reset_driver); + +MODULE_AUTHOR("Thor Thayer "); +MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver"); +MODULE_LICENSE("GPL v2");