From patchwork Wed Mar 15 13:31:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9625651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A7D17604A9 for ; Wed, 15 Mar 2017 13:33:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 980E228304 for ; Wed, 15 Mar 2017 13:33:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CAFB2861A; Wed, 15 Mar 2017 13:33:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4056A28304 for ; Wed, 15 Mar 2017 13:33:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8sDEjmVLFsgQvVViygqIkS5nHqlKjTfEkj6CFfMuGgw=; b=oZqihUu4k754o7 ofg92EUzCsgFKmNwoegszBoQYYjtK1pOwEukSzGTSIpMsVvs8z2vKDCodio4nHczvkbc3f/3zK8iZ gXEtaLhYNGkK3XRH49Aow5WRU88VsGiM3bd+xCFegHTxONpOh4mVRtgY8nzcL1djLZWLfYg+WhPLj dTbI3FmlFU7g4fpaIzdKv4SCN/gNfQr0EEPx7uXcS7WzOCwynXwK85bwoND4FY3Yodoe6aqXKv45j mSJLUtgLYDJIv66RSWB6wjdnuKgAHxed08jGQ5u13apXxeO4lwPwoIEXienZ1wMy8ejof66IxDIyw jBamDV2jqm6aeUG6iLEA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1co939-0007rc-Sn; Wed, 15 Mar 2017 13:33:11 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1co92U-00072P-6g for linux-arm-kernel@lists.infradead.org; Wed, 15 Mar 2017 13:32:34 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 15 Mar 2017 06:32:05 -0700 Received: from HQMAIL105.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 15 Mar 2017 06:32:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 15 Mar 2017 06:32:12 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 15 Mar 2017 13:32:12 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 15 Mar 2017 13:32:12 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Wed, 15 Mar 2017 13:32:12 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.151]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 15 Mar 2017 06:32:11 -0700 From: Jon Hunter To: Thierry Reding Subject: [PATCH 3/5] soc/tegra: Move Tegra flowctrl driver Date: Wed, 15 Mar 2017 13:31:53 +0000 Message-ID: <1489584715-23138-4-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489584715-23138-1-git-send-email-jonathanh@nvidia.com> References: <1489584715-23138-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170315_063230_290897_79259DF3 X-CRM114-Status: GOOD ( 23.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , Jon Hunter , Rob Herring , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter --- arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/cpuidle-tegra20.c | 3 +- arch/arm/mach-tegra/flowctrl.c | 177 -------------------------------- arch/arm/mach-tegra/flowctrl.h | 66 ------------ arch/arm/mach-tegra/platsmp.c | 2 +- arch/arm/mach-tegra/pm.c | 2 +- arch/arm/mach-tegra/reset-handler.S | 2 +- arch/arm/mach-tegra/sleep-tegra20.S | 3 +- arch/arm/mach-tegra/sleep-tegra30.S | 2 +- arch/arm/mach-tegra/tegra.c | 2 - drivers/soc/tegra/Kconfig | 5 + drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/flowctrl.c | 186 ++++++++++++++++++++++++++++++++++ include/soc/tegra/flowctrl.h | 62 ++++++++++++ 15 files changed, 263 insertions(+), 252 deletions(-) delete mode 100644 arch/arm/mach-tegra/flowctrl.c delete mode 100644 arch/arm/mach-tegra/flowctrl.h create mode 100644 drivers/soc/tegra/flowctrl.c create mode 100644 include/soc/tegra/flowctrl.h diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 329f01c5b6f8..5de9104ee15e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -13,5 +13,6 @@ menuconfig ARCH_TEGRA select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER select SOC_BUS + select SOC_TEGRA_FLOWCTRL help This enables support for NVIDIA Tegra based systems. diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fffad2426ee4..3b33f0bb78ae 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -2,7 +2,6 @@ asflags-y += -march=armv7-a obj-y += io.o obj-y += irq.o -obj-y += flowctrl.o obj-y += pm.o obj-y += reset.o obj-y += reset-handler.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index afcee04f2616..76e4c83cd5c8 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -26,12 +26,13 @@ #include #include +#include + #include #include #include #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c deleted file mode 100644 index 40b15e39f849..000000000000 --- a/arch/arm/mach-tegra/flowctrl.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.c - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "flowctrl.h" - -static u8 flowctrl_offset_halt_cpu[] = { - FLOW_CTRL_HALT_CPU0_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS + 8, - FLOW_CTRL_HALT_CPU1_EVENTS + 16, -}; - -static u8 flowctrl_offset_cpu_csr[] = { - FLOW_CTRL_CPU0_CSR, - FLOW_CTRL_CPU1_CSR, - FLOW_CTRL_CPU1_CSR + 8, - FLOW_CTRL_CPU1_CSR + 16, -}; - -static void __iomem *tegra_flowctrl_base; - -static void flowctrl_update(u8 offset, u32 value) -{ - if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) - return; - - writel(value, tegra_flowctrl_base + offset); - - /* ensure the update has reached the flow controller */ - wmb(); - readl_relaxed(tegra_flowctrl_base + offset); -} - -u32 flowctrl_read_cpu_csr(unsigned int cpuid) -{ - u8 offset = flowctrl_offset_cpu_csr[cpuid]; - - if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) - return 0; - - return readl(tegra_flowctrl_base + offset); -} - -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); -} - -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) -{ - return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); -} - -void flowctrl_cpu_suspend_enter(unsigned int cpuid) -{ - unsigned int reg; - int i; - - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfe */ - reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - /* pwr gating on wfi */ - reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; - break; - } - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ - reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ - flowctrl_write_cpu_csr(cpuid, reg); - - for (i = 0; i < num_possible_cpus(); i++) { - if (i == cpuid) - continue; - reg = flowctrl_read_cpu_csr(i); - reg |= FLOW_CTRL_CSR_EVENT_FLAG; - reg |= FLOW_CTRL_CSR_INTR_FLAG; - flowctrl_write_cpu_csr(i, reg); - } -} - -void flowctrl_cpu_suspend_exit(unsigned int cpuid) -{ - unsigned int reg; - - /* Disable powergating via flow controller for CPU0 */ - reg = flowctrl_read_cpu_csr(cpuid); - switch (tegra_get_chip_id()) { - case TEGRA20: - /* clear wfe bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; - break; - case TEGRA30: - case TEGRA114: - case TEGRA124: - /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; - /* clear wfi bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; - break; - } - reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ - flowctrl_write_cpu_csr(cpuid, reg); -} - -static const struct of_device_id matches[] __initconst = { - { .compatible = "nvidia,tegra124-flowctrl" }, - { .compatible = "nvidia,tegra114-flowctrl" }, - { .compatible = "nvidia,tegra30-flowctrl" }, - { .compatible = "nvidia,tegra20-flowctrl" }, - { } -}; - -void __init tegra_flowctrl_init(void) -{ - /* hardcoded fallback if device tree node is missing */ - unsigned long base = 0x60007000; - unsigned long size = SZ_4K; - struct device_node *np; - - np = of_find_matching_node(NULL, matches); - if (np) { - struct resource res; - - if (of_address_to_resource(np, 0, &res) == 0) { - size = resource_size(&res); - base = res.start; - } - - of_node_put(np); - } - - tegra_flowctrl_base = ioremap_nocache(base, size); -} diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h deleted file mode 100644 index 73a9c5016c1a..000000000000 --- a/arch/arm/mach-tegra/flowctrl.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-tegra/flowctrl.h - * - * functions and macros to control the flowcontroller - * - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __MACH_TEGRA_FLOWCTRL_H -#define __MACH_TEGRA_FLOWCTRL_H - -#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTRL_WAITEVENT (2 << 29) -#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) -#define FLOW_CTRL_JTAG_RESUME (1 << 28) -#define FLOW_CTRL_SCLK_RESUME (1 << 27) -#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) -#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) -#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) -#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) -#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) -#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) -#define FLOW_CTRL_CPU0_CSR 0x8 -#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) -#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) -#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) -#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) -#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ - FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ - FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) -#define FLOW_CTRL_CSR_ENABLE (1 << 0) -#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTRL_CPU1_CSR 0x18 - -#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) -#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 - -#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) -#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) -#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) - -#ifndef __ASSEMBLY__ -u32 flowctrl_read_cpu_csr(unsigned int cpuid); -void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); -void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); - -void flowctrl_cpu_suspend_enter(unsigned int cpuid); -void flowctrl_cpu_suspend_exit(unsigned int cpuid); - -void tegra_flowctrl_init(void); -#endif - -#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 75620ae73913..b5a2afe99101 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -30,7 +31,6 @@ #include #include "common.h" -#include "flowctrl.h" #include "iomap.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index b0f48a3946fa..1ad5719779b0 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -38,7 +39,6 @@ #include #include -#include "flowctrl.h" #include "iomap.h" #include "pm.h" #include "reset.h" diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e3070fdab80b..805f306fa6f7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -17,12 +17,12 @@ #include #include +#include #include #include #include -#include "flowctrl.h" #include "iomap.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index f5d19667484e..5c8e638ee51a 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -20,6 +20,8 @@ #include +#include + #include #include #include @@ -27,7 +29,6 @@ #include "irammap.h" #include "sleep.h" -#include "flowctrl.h" #define EMC_CFG 0xc #define EMC_ADR_CFG 0x10 diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 16e5ff03383c..dd4a67dabd91 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -16,13 +16,13 @@ #include +#include #include #include #include #include -#include "flowctrl.h" #include "irammap.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e01cbca196b5..649e9e8c7bcc 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -48,7 +48,6 @@ #include "board.h" #include "common.h" #include "cpuidle.h" -#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" @@ -75,7 +74,6 @@ static void __init tegra_init_early(void) { of_register_trusted_foundations(); tegra_cpu_reset_handler_init(); - tegra_flowctrl_init(); } static void __init tegra_dt_init_irq(void) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 208d6edb3fdb..28785814fe22 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -59,6 +59,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for NVIDIA Tegra132 SoC, based on the Denver @@ -69,6 +70,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, @@ -101,6 +103,9 @@ config ARCH_TEGRA_186_SOC endif endif +config SOC_TEGRA_FLOWCTRL + bool + config SOC_TEGRA_PMC bool diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index b4425e4319ff..4f81dd55e5d1 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -1,5 +1,6 @@ obj-y += fuse/ obj-y += common.o +obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c new file mode 100644 index 000000000000..b94d9161e448 --- /dev/null +++ b/drivers/soc/tegra/flowctrl.c @@ -0,0 +1,186 @@ +/* + * drivers/soc/tegra/flowctrl.c + * + * Functions and macros to control the flowcontroller + * + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static u8 flowctrl_offset_halt_cpu[] = { + FLOW_CTRL_HALT_CPU0_EVENTS, + FLOW_CTRL_HALT_CPU1_EVENTS, + FLOW_CTRL_HALT_CPU1_EVENTS + 8, + FLOW_CTRL_HALT_CPU1_EVENTS + 16, +}; + +static u8 flowctrl_offset_cpu_csr[] = { + FLOW_CTRL_CPU0_CSR, + FLOW_CTRL_CPU1_CSR, + FLOW_CTRL_CPU1_CSR + 8, + FLOW_CTRL_CPU1_CSR + 16, +}; + +static void __iomem *tegra_flowctrl_base; + +static void flowctrl_update(u8 offset, u32 value) +{ + if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) + return; + + writel(value, tegra_flowctrl_base + offset); + + /* ensure the update has reached the flow controller */ + wmb(); + readl_relaxed(tegra_flowctrl_base + offset); +} + +u32 flowctrl_read_cpu_csr(unsigned int cpuid) +{ + u8 offset = flowctrl_offset_cpu_csr[cpuid]; + + if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) + return 0; + + return readl(tegra_flowctrl_base + offset); +} + +void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) +{ + return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value); +} + +void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) +{ + return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value); +} + +void flowctrl_cpu_suspend_enter(unsigned int cpuid) +{ + unsigned int reg; + int i; + + reg = flowctrl_read_cpu_csr(cpuid); + switch (tegra_get_chip_id()) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfe */ + reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; + break; + case TEGRA30: + case TEGRA114: + case TEGRA124: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfi */ + reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; + break; + } + reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ + reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ + reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ + flowctrl_write_cpu_csr(cpuid, reg); + + for (i = 0; i < num_possible_cpus(); i++) { + if (i == cpuid) + continue; + reg = flowctrl_read_cpu_csr(i); + reg |= FLOW_CTRL_CSR_EVENT_FLAG; + reg |= FLOW_CTRL_CSR_INTR_FLAG; + flowctrl_write_cpu_csr(i, reg); + } +} + +void flowctrl_cpu_suspend_exit(unsigned int cpuid) +{ + unsigned int reg; + + /* Disable powergating via flow controller for CPU0 */ + reg = flowctrl_read_cpu_csr(cpuid); + switch (tegra_get_chip_id()) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + break; + case TEGRA30: + case TEGRA114: + case TEGRA124: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + break; + } + reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ + reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ + reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ + flowctrl_write_cpu_csr(cpuid, reg); +} + +static const struct of_device_id matches[] __initconst = { + { .compatible = "nvidia,tegra124-flowctrl" }, + { .compatible = "nvidia,tegra114-flowctrl" }, + { .compatible = "nvidia,tegra30-flowctrl" }, + { .compatible = "nvidia,tegra20-flowctrl" }, + { } +}; + +static int __init tegra_flowctrl_init(void) +{ + /* hardcoded fallback if device tree node is missing */ + unsigned long base = 0x60007000; + unsigned long size = SZ_4K; + struct device_node *np; + + if (!soc_is_tegra()) + return 0; + + np = of_find_matching_node(NULL, matches); + if (np) { + struct resource res; + + if (of_address_to_resource(np, 0, &res) == 0) { + size = resource_size(&res); + base = res.start; + } + + of_node_put(np); + } + + tegra_flowctrl_base = ioremap_nocache(base, size); + + if (!tegra_flowctrl_base) + return -ENXIO; + + return 0; +} +early_initcall(tegra_flowctrl_init); diff --git a/include/soc/tegra/flowctrl.h b/include/soc/tegra/flowctrl.h new file mode 100644 index 000000000000..034ce0ec713f --- /dev/null +++ b/include/soc/tegra/flowctrl.h @@ -0,0 +1,62 @@ +/* + * Functions and macros to control the flowcontroller + * + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __SOC_TEGRA_FLOWCTRL_H__ +#define __SOC_TEGRA_FLOWCTRL_H__ + +#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTRL_WAITEVENT (2 << 29) +#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_SCLK_RESUME (1 << 27) +#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) +#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) +#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) +#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) +#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) +#define FLOW_CTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) +#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) +#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) +#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ + FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ + FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) +#define FLOW_CTRL_CSR_ENABLE (1 << 0) +#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTRL_CPU1_CSR 0x18 + +#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 + +#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) +#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) +#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) + +#ifndef __ASSEMBLY__ +u32 flowctrl_read_cpu_csr(unsigned int cpuid); +void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); +void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); + +void flowctrl_cpu_suspend_enter(unsigned int cpuid); +void flowctrl_cpu_suspend_exit(unsigned int cpuid); +#endif + +#endif