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Fri, 7 Apr 2017 17:10:22 +0200 From: Alexandre TORGUE To: Linus Walleij , Maxime Coquelin , Patrice Chotard , Paul Gortmaker , Rob Herring Subject: [PATCH 1/4] pinctrl: stm32: set pin to gpio input when used as interrupt Date: Fri, 7 Apr 2017 17:10:08 +0200 Message-ID: <1491577811-26989-2-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491577811-26989-1-git-send-email-alexandre.torgue@st.com> References: <1491577811-26989-1-git-send-email-alexandre.torgue@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-07_12:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170407_111051_219699_C9D90D1B X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch ensures that pin is correctly set as gpio input when it is used as an interrupt. Signed-off-by: Alexandre TORGUE diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index abc405b..c8825e5 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -207,12 +207,35 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) .to_irq = stm32_gpio_to_irq, }; +static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + u32 ret; + + if (!gpiochip_is_requested(&bank->gpio_chip, irq_data->hwirq)) { + ret = stm32_gpio_request(&bank->gpio_chip, irq_data->hwirq); + if (ret) + return ret; + } + + return stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); +} + +static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + + stm32_gpio_free(&bank->gpio_chip, irq_data->hwirq); +} + static struct irq_chip stm32_gpio_irq_chip = { .name = "stm32gpio", .irq_eoi = irq_chip_eoi_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, .irq_set_type = irq_chip_set_type_parent, + .irq_request_resources = stm32_gpio_irq_request_resources, + .irq_release_resources = stm32_gpio_irq_release_resources, }; static int stm32_gpio_domain_translate(struct irq_domain *d,