From patchwork Mon May 22 12:48:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 9740101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 55854601C2 for ; Mon, 22 May 2017 12:18:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43688284C0 for ; Mon, 22 May 2017 12:18:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 36F3A28697; Mon, 22 May 2017 12:18:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9FC0C284C0 for ; Mon, 22 May 2017 12:18:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=3i9vCrsI4M6N2RJkmkUtDf6BYPDOOR+EwteQz4H4aGI=; b=QUlidvYKTPCJrC KDzjkY3bakeUN/uHPr/izjj5Q+Ksuz4ehn9BTfNSDeUz41mQXCk5gkJKk1CGr8h6gDz7Lw8KYlIY6 +KFZPka0fukBxJySQUDHtc8ZvBnPuwkRbmtNJ2E22LuBIhnTJiM9dEDcNiKQyb+slIQAouTHhmOSU c5MByHJB4xXW44nEXJVmTdjDJra1+Q0GUZ8nrZXVrvX810ItV3H/KX+OgRwmpAQMfrtoNpQBoMX8N TEnhYmxd0zYoc45BIhQddFqrXWYB0AnrGaxfhWn/8JrGnCG+7syLNfI4PI6SJfGvZks41Ph8DsbKu tR6iwpxwXRIAsA9ZS5vg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dCmI1-0004q0-UW; Mon, 22 May 2017 12:18:21 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dCmHR-00042b-W0 for linux-arm-kernel@lists.infradead.org; Mon, 22 May 2017 12:17:51 +0000 Received: from 172.30.72.57 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOA30810; Mon, 22 May 2017 20:17:20 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Mon, 22 May 2017 20:17:14 +0800 From: Shaokun Zhang To: , , Subject: [PATCH v8 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Date: Mon, 22 May 2017 20:48:21 +0800 Message-ID: <1495457301-234856-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5922D6D1.0191, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f4f41975d55f96851d1b7c06ae072cdd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170522_051746_845007_5AB3B28F X-CRM114-Status: GOOD ( 13.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dikshit.n@huawei.com, devicetree@vger.kernel.org, wangkefeng.wang@huawei.com, anurupvasu@gmail.com, gabriele.paoloni@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, shyju.pv@huawei.com, linux-kernel@vger.kernel.org, xuwei5@hisilicon.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, sanil.kumar@hisilicon.com, linux-arm-kernel@lists.infradead.org, shiju.jose@huawei.com, tanxiaojun@huawei.com, anurup.m@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Anurup M 1) Device tree bindings for Hisilicon SoC PMU. 2) Add example for Hisilicon L3 cache and MN PMU. 3) Add child nodes of L3C and MN in djtag bindings example. Signed-off-by: Anurup M Signed-off-by: Shaokun Zhang Acked-by: Rob Herring --- .../devicetree/bindings/arm/hisilicon/djtag.txt | 29 +++++++ .../devicetree/bindings/arm/hisilicon/pmu.txt | 93 ++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt index fde5bab..27e67cc 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt @@ -27,6 +27,35 @@ Example 1: Djtag for CPU die in HiP07 hisilicon,scl-id = <0x03>; /* All connecting components will appear as child nodes */ + + pmul3c0 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x01>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c1 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x02>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c2 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x03>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c3 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x04>; + hisilicon,instance-id = <0x01>; + }; + + pmumn0 { + compatible = "hisilicon,hip07-pmu-mn-v2"; + hisilicon,module-id = <0x21>; + }; }; Hisilicon HiP05/06/07 djtag for IO die diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt new file mode 100644 index 0000000..488e740 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt @@ -0,0 +1,93 @@ +Hisilicon SoC HiP05/06/07 ARMv8 PMU +=================================== + +The Hisilicon SoC chips like HiP05/06/07 etc. consist of various independent +system device PMUs such as L3 cache (L3C) and Miscellaneous Nodes(MN). These +PMU devices are independent and have hardware logic to gather statistics and +performance information. + +HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +in HiP05/06/07 chips are further grouped as CPU clusters (CCL) which includes +4 cpu-cores each. +e.g. In the case of HiP05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device. +The L3 cache is further grouped as 4 L3 cache banks in a SCCL. + +The Hisilicon SoC PMU DT node bindings for uncore PMU devices are as below. +For PMU devices like L3 cache. MN etc. which are accessed using the djtag, +the parent node will be the djtag node of the corresponding CPU die (SCCL). + +L3 cache +--------- +The L3 cache is dedicated for each SCCL. Each SCCL in HiP05/06/07 chips have 4 +L3 cache banks. Each L3 cache bank have separate DT nodes. + +Required properties: + + - compatible : This value should be as follows + (a) "hisilicon,hip05-pmu-l3c-v1" for v1 hw in HiP05 chipset + (b) "hisilicon,hip06-pmu-l3c-v1" for v1 hw in HiP06 chipset + (c) "hisilicon,hip07-pmu-l3c-v2" for v2 hw in HiP07 chipset + + - hisilicon,module-id : This property is the module identifier for djtag. + In v1 hw, this value is 0x04 for all L3 cache instances. But + in v2 hw, this value is unique for each L3 cache instance. + + - hisilicon,instance-id : This property will identify the L3 cache instance + or bank in djtag. In v1 hw, this value is unique for each L3 cache + instance. But in v2 hw, it is 0x01 for all L3 cache instances. + + *The counter overflow IRQ is not supported in v1, v2 hardware (HiP05/06/07). + +Miscellaneous Node +------------------ +The MN is dedicated for each SCCL and hence there are separate DT nodes for MN +for each SCCL. + +Required properties: + + - compatible : This value should be as follows + (a) "hisilicon,hip05-pmu-mn-v1" for v1 hw in HiP05 chipset + (b) "hisilicon,hip06-pmu-mn-v1" for v1 hw in HiP06 chipset + (c) "hisilicon,hip07-pmu-mn-v2" for v2 hw in HiP07 chipset + + - hisilicon,module-id : Module ID to input for djtag. + + *The counter overflow IRQ is not supported in v1, v2 hardware (HiP05/06/07). + +Example: + + djtag0: djtag@60010000 { + compatible = "hisilicon,hip07-cpu-djtag-v2"; + reg = <0x0 0x60010000 0x0 0x10000>; + hisilicon,scl-id = <0x03>; + + pmul3c0 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x01>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c1 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x02>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c2 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x03>; + hisilicon,instance-id = <0x01>; + }; + + pmul3c3 { + compatible = "hisilicon,hip07-pmu-l3c-v2"; + hisilicon,module-id = <0x04>; + hisilicon,instance-id = <0x01>; + }; + + pmumn0 { + compatible = "hisilicon,hip07-pmu-mn-v2"; + hisilicon,module-id = <0x21>; + }; + };