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Mon, 29 May 2017 11:28:35 +0200 From: Fabrice Gasnier To: , , , , , Subject: [PATCH v2 4/5] iio: adc: stm32: make per instance bus clock optional Date: Mon, 29 May 2017 11:28:19 +0200 Message-ID: <1496050100-25854-5-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496050100-25854-1-git-send-email-fabrice.gasnier@st.com> References: <1496050100-25854-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-29_06:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170529_052922_248986_D01E1BDC X-CRM114-Status: GOOD ( 15.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, benjamin.gaignard@linaro.org, lars@metafoo.de, alexandre.torgue@st.com, linux-iio@vger.kernel.org, pmeerw@pmeerw.net, mcoquelin.stm32@gmail.com, knaack.h@gmx.de, fabrice.gasnier@st.com, benjamin.gaignard@st.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP STM32F4 requires one clock per ADC instance for register access. But, newer version of ADC hardware block have common bus clock for all instances (per instance driver isn't responsible for getting it). So, make it optional by default. Still, enforce it's required on STM32F4. Signed-off-by: Fabrice Gasnier --- drivers/iio/adc/stm32-adc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index 50b2538..2ba9ca9 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -160,6 +160,7 @@ struct stm32_adc_regspec { * @regs: registers descriptions * @adc_info: per instance input channels definitions * @trigs: external trigger sources + * @clk_required: clock is required * @start_conv: routine to start conversions * @stop_conv: routine to stop conversions */ @@ -167,6 +168,7 @@ struct stm32_adc_cfg { const struct stm32_adc_regspec *regs; const struct stm32_adc_info *adc_info; struct stm32_adc_trig_info *trigs; + bool clk_required; void (*start_conv)(struct stm32_adc *, bool dma); void (*stop_conv)(struct stm32_adc *); }; @@ -1145,14 +1147,21 @@ static int stm32_adc_probe(struct platform_device *pdev) adc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(adc->clk)) { - dev_err(&pdev->dev, "Can't get clock\n"); - return PTR_ERR(adc->clk); + ret = PTR_ERR(adc->clk); + if (ret == -ENOENT && !adc->cfg->clk_required) { + adc->clk = NULL; + } else { + dev_err(&pdev->dev, "Can't get clock\n"); + return ret; + } } - ret = clk_prepare_enable(adc->clk); - if (ret < 0) { - dev_err(&pdev->dev, "clk enable failed\n"); - return ret; + if (adc->clk) { + ret = clk_prepare_enable(adc->clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk enable failed\n"); + return ret; + } } ret = stm32_adc_of_get_resolution(indio_dev); @@ -1196,7 +1205,8 @@ static int stm32_adc_probe(struct platform_device *pdev) dma_release_channel(adc->dma_chan); } err_clk_disable: - clk_disable_unprepare(adc->clk); + if (adc->clk) + clk_disable_unprepare(adc->clk); return ret; } @@ -1214,7 +1224,8 @@ static int stm32_adc_remove(struct platform_device *pdev) adc->rx_buf, adc->rx_dma_buf); dma_release_channel(adc->dma_chan); } - clk_disable_unprepare(adc->clk); + if (adc->clk) + clk_disable_unprepare(adc->clk); return 0; } @@ -1223,6 +1234,7 @@ static int stm32_adc_remove(struct platform_device *pdev) .regs = &stm32f4_adc_regspec, .adc_info = &stm32f4_adc_info, .trigs = stm32f4_adc_trigs, + .clk_required = true, .start_conv = stm32f4_adc_start_conv, .stop_conv = stm32f4_adc_stop_conv, };