From patchwork Tue May 30 09:16:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 9754179 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D4D56602BF for ; Tue, 30 May 2017 09:17:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C67D027569 for ; Tue, 30 May 2017 09:17:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA6A927F10; Tue, 30 May 2017 09:17:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4411927569 for ; Tue, 30 May 2017 09:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=shhMfuGJzEN/T4xfG+B1Oo90iPlGy+fw77dfjfNTJj0=; b=K7D4ZJmqsb9OdUXBNaNqJ2a3IY bISLEqSzISg+pZpdpkioX+fpIMHiDOmxh2VBGrv9buywn+sPrquH3NvQ8D66AHgqOQCFjpreRQd8/ L081qKVoWL8D4jSSs9WH+ADiSeGesshdrdkuyDETiS7O2epXtdTQBHvHB7Giwr3zlO5rrBC2GCpf3 edqIlw9YIdbsXAmMax1uKUdpxZrJqJE3mbaut9sTDzg7Es9sbpc77veQKcHlaMwvNqdc3ZaS+BzIb bPmXGwPRqwI8QLWjwesUMR0szQ1n5/dblYMK6q0J89sYOBO/H2pIMAa/kKBtnijkpeCQx2vLCQhOv Jo/Y0E6g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dFdHb-0002to-OK; Tue, 30 May 2017 09:17:43 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dFdGl-00021e-07 for linux-arm-kernel@lists.infradead.org; Tue, 30 May 2017 09:16:54 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id E0E2E20EDC; Tue, 30 May 2017 11:16:28 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B71F320411; Tue, 30 May 2017 11:16:28 +0200 (CEST) From: Thomas Petazzoni To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Subject: [PATCH 2/6] dt-bindings: interrupt-controller: add DT binding for the Marvell ICU Date: Tue, 30 May 2017 11:16:07 +0200 Message-Id: <1496135772-20694-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170530_021651_366037_3CFD4683 X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Yehuda Yitschak , Antoine Tenart , Nadav Haklai , Hanna Hawa , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the Device Tree binding documentation for the Marvell ICU interrupt controller, which collects wired interrupts from the devices located into the CP110 hardware block of Marvell Armada 7K/8K, and converts them into SPI interrupts in the GIC located in the AP hardware block, using the GICP extension. Signed-off-by: Thomas Petazzoni --- .../bindings/interrupt-controller/marvell,icu.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt new file mode 100644 index 0000000..e0b4068 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt @@ -0,0 +1,57 @@ +Marvell ICU Interrupt Controller +-------------------------------- + +The Marvell ICU (Interrupt Consolidation Unit) controller is +responsible for collecting all wired-interrupt sources in the CP and +communicating them to the GIC in the AP, the unit translates interrupt +requests on input wires to MSG memory mapped transactions to the GIC. + +The interrupts from the ICU to the GIC can be mapped to one of the following groups: + +- Shared Peripheral Interrupt - Non-Secured (SPI_NSR) +- Shared Peripheral Interrupt - Secured (SPI_SR) +- System Error Interrupt (SEI) +- RAM Error Interrupt (REI) + +Required properties: + +- compatible: Should be "marvell,icu" + +- reg: Should contain ICU registers location and length. + +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be + 3. + + The 1st cell is the group type of the ICU interrupt (SPI_NSR, + SPI_SR, SEI, and REI). + + The 2nd cell is the index of the interrupt in the ICU unit. + + The 3rd cell is the type of the interrupt. See arm,gic.txt for + details. + +- interrupt-controller: Identifies the node as an interrupt + controller. + +- interrupt-parent: Indicates the node of the parent interrupt + controller. Should be pointer to the GIC. + +- gicp: Should point to the GICP controller, the GIC extension that + allows to trigger interrupts using MSG memory mapped transactions. + +Example: + +icu: interrupt-controller@1e0000 { + compatible = "marvell,icu"; + reg = <0x1e0000 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + gicp = <&gicp>; +}; + +usb3h0: usb3@500000 { + interrupt-parent = <&icu>; + interrupts = ; +};