| Message ID | 1496368045-17746-3-git-send-email-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Freitag, 2. Juni 2017, 09:47:24 CEST schrieb Elaine Zhang: > Add devicetree bindings for Rockchip cru which found on > Rockchip SoCs. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> the binding + binding header did receive an Acked-by: Rob Herring <robh@kernel.org> in v1 already. Please carry these over when sending new versions. [no need to do that for your v4 now though :-) ] > --- > .../bindings/clock/rockchip,rk3128-cru.txt | 56 ++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt > new file mode 100644 > index 000000000000..455a9a00a623 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt > @@ -0,0 +1,56 @@ > +* Rockchip RK3128 Clock and Reset Unit > + > +The RK3128 clock controller generates and supplies clock to various > +controllers within the SoC and also implements a reset controller for SoC > +peripherals. > + > +Required Properties: > + > +- compatible: should be "rockchip,rk3128-cru" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- #clock-cells: should be 1. > +- #reset-cells: should be 1. > + > +Optional Properties: > + > +- rockchip,grf: phandle to the syscon managing the "general register files" > + If missing pll rates are not changeable, due to the missing pll lock status. > + > +Each clock is assigned an identifier and client nodes can use this identifier > +to specify the clock which they consume. All available clocks are defined as > +preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be > +used in device tree sources. Similar macros exist for the reset sources in > +these files. > + > +External clocks: > + > +There are several clocks that are generated outside the SoC. It is expected > +that they are defined using standard clock bindings with following > +clock-output-names: > + - "xin24m" - crystal input - required, > + - "ext_i2s" - external I2S clock - optional, > + - "gmac_clkin" - external GMAC clock - optional > + > +Example: Clock controller node: > + > + cru: cru@20000000 { > + compatible = "rockchip,rk3128-cru"; > + reg = <0x20000000 0x1000>; > + rockchip,grf = <&grf>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > +Example: UART controller node that consumes the clock generated by the clock > + controller: > + > + uart2: serial@20068000 { > + compatible = "rockchip,serial"; > + reg = <0x20068000 0x100>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <24000000>; > + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; > + clock-names = "sclk_uart", "pclk_uart"; > + }; >
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt new file mode 100644 index 000000000000..455a9a00a623 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt @@ -0,0 +1,56 @@ +* Rockchip RK3128 Clock and Reset Unit + +The RK3128 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3128-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "gmac_clkin" - external GMAC clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart2: serial@20068000 { + compatible = "rockchip,serial"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "sclk_uart", "pclk_uart"; + };
Add devicetree bindings for Rockchip cru which found on Rockchip SoCs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../bindings/clock/rockchip,rk3128-cru.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt