From patchwork Tue Jun 13 09:05:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 9783383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F2C5160325 for ; Tue, 13 Jun 2017 09:06:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E830027FB7 for ; Tue, 13 Jun 2017 09:06:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD0D2283AE; Tue, 13 Jun 2017 09:06:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2AD3E27FB7 for ; Tue, 13 Jun 2017 09:06:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1lLyuEqOsPcqVppCytyBiEhBcE4B+yvy2WGEGaSJxEc=; b=HsZnXMjOy/meNV 0xIBZEqV49BhxpjF2Psz6y0NF0FZ+Adci2sYJprsM+gMxWkcuHlbQECCp3K+efj7RpEvkaLQhPINJ x0viiz74utGd22s4C/q/9T5yi8DBG1uWZ7LodJp0S9P6utQ84sBsmWUHo0SoF0+J8I9gVwbhqtoA+ EHJNp0kKI/nRtOTqdEKxZ0YdMh7mY1IGglMWd8JZtXsLdmWobJgCrCTycrD/oz/9uffsZd4490adD D+vC0tspJ7HADoRqbox0yequZsyRR6o/Ufj475VroyeTYc+Rlbu8lIvRYm26GZeRFN9zMV66OnWIh qehcse2Eejtoc1NzF+Ug==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dKhmG-0004Gr-MQ; Tue, 13 Jun 2017 09:06:20 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dKhlk-0003kp-37 for linux-arm-kernel@lists.infradead.org; Tue, 13 Jun 2017 09:05:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 249EC15B2; Tue, 13 Jun 2017 02:05:31 -0700 (PDT) Received: from bc-e9-2-15.euhpc.arm.com. (bc-e9-2-15.euhpc.arm.com [10.6.2.247]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CB33E3F581; Tue, 13 Jun 2017 02:05:29 -0700 (PDT) From: Vladimir Murzin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/7] ARM: NOMMU: Update MPU accessors to use cp15 helpers Date: Tue, 13 Jun 2017 10:05:02 +0100 Message-Id: <1497344707-14446-3-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1497344707-14446-1-git-send-email-vladimir.murzin@arm.com> References: <1497344707-14446-1-git-send-email-vladimir.murzin@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170613_020548_274016_97845316 X-CRM114-Status: UNSURE ( 7.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexandre.torgue@st.com, manabian@gmail.com, linux@armlinux.org.uk, stefan@agner.ch, kbuild-all@01.org, u.kleine-koenig@pengutronix.de, sza@esh.hu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, inline assembly for accessing to MPU's cp15 lacks volatile keyword which opens possibility to compiler to optimise such accesses as soon as we start using them more intensively. Rather than fixing inline asm, lets move MPU accessors to use cp15 helpers which do the right thing. Tested-by: Szemző András Signed-off-by: Vladimir Murzin --- arch/arm/mm/pmsa-v7.c | 48 ++++++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index ee3cf51..5b55f8f 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -12,63 +12,67 @@ #include "mm.h" +#define DRBAR __ACCESS_CP15(c6, 0, c1, 0) +#define IRBAR __ACCESS_CP15(c6, 0, c1, 1) +#define DRSR __ACCESS_CP15(c6, 0, c1, 2) +#define IRSR __ACCESS_CP15(c6, 0, c1, 3) +#define DRACR __ACCESS_CP15(c6, 0, c1, 4) +#define IRACR __ACCESS_CP15(c6, 0, c1, 5) +#define RNGNR __ACCESS_CP15(c6, 0, c2, 0) + /* Region number */ -static void rgnr_write(u32 v) +static inline void rgnr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v)); + write_sysreg(v, RNGNR); } /* Data-side / unified region attributes */ /* Region access control register */ -static void dracr_write(u32 v) +static inline void dracr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v)); + write_sysreg(v, DRACR); } /* Region size register */ -static void drsr_write(u32 v) +static inline void drsr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v)); + write_sysreg(v, DRSR); } /* Region base address register */ -static void drbar_write(u32 v) +static inline void drbar_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v)); + write_sysreg(v, DRBAR); } -static u32 drbar_read(void) +static inline u32 drbar_read(void) { - u32 v; - asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v)); - return v; + return read_sysreg(DRBAR); } /* Optional instruction-side region attributes */ /* I-side Region access control register */ -static void iracr_write(u32 v) +static inline void iracr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v)); + write_sysreg(v, IRACR); } /* I-side Region size register */ -static void irsr_write(u32 v) +static inline void irsr_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v)); + write_sysreg(v, IRSR); } /* I-side Region base address register */ -static void irbar_write(u32 v) +static inline void irbar_write(u32 v) { - asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v)); + write_sysreg(v, IRBAR); } -static unsigned long irbar_read(void) +static inline u32 irbar_read(void) { - unsigned long v; - asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v)); - return v; + return read_sysreg(IRBAR); } /* MPU initialisation functions */