From patchwork Thu Jun 22 17:44:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 9805023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1E4D6600C5 for ; Thu, 22 Jun 2017 17:45:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09A58285D1 for ; Thu, 22 Jun 2017 17:45:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F20DE286FC; Thu, 22 Jun 2017 17:45:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 11E40285D1 for ; Thu, 22 Jun 2017 17:45:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=eJN1+ec55QZ0Bu8FUepiYyTFa0xJoXIzIB8U+vpHjTc=; b=FxN 49gURwU3kp0RW2ataaoclASKGsw/M1TzOKE+tV1aYti3CsLFCExhNAwlYnuZkp9lUi52XDSQ87oIb CLXXXi8bAeJcmz2AKPkCZUUSZjGbtW+2SE1rOOK80YAjvZVu8UZ7t9JRsZJ5b2svXiENZoktUu8sR btD//FObUTNXi8mkZJ/depLEpZw3Y8tU+qnM6yXt+mJWZd67599Kjv70H4R3FZ4RhldvFiC7GrWkt iFIHBj7dR5i6FWJkYhXZK0kLUn6r7jVCDlRHq2HHf8+2WYKczEctcL9pKXTVWnxs9ycEPDjec4bT+ f2v9Sox17pMhvQV+hU51mMwEXtst6JA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dO6Al-0007ZV-9Z; Thu, 22 Jun 2017 17:45:39 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dO6Ah-0007Yk-IO for linux-arm-kernel@lists.infradead.org; Thu, 22 Jun 2017 17:45:37 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C03B760A52; Thu, 22 Jun 2017 17:45:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498153512; bh=eFFAjuGIO6YGDFBR8KWp4xU9aZaSLisdXDlQeBDs05k=; h=From:To:Cc:Subject:Date:From; b=bJSufapp1OikGKm4U6KgKlRryFTDaYNKdwm57JwyjwXzEAr6tYuSBTDggbRx4PpDp pa0uaEkeVNab/G/UpFTnfCieCFtxgpxjtoap1nzfQvisVXzE9BfdPhvmtfQpsJQPpH Nczkg1iQDb6aLUPqs9Mz0/Xoyi9WFhejDSOcYdtw= Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D629A60132; Thu, 22 Jun 2017 17:45:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498153511; bh=eFFAjuGIO6YGDFBR8KWp4xU9aZaSLisdXDlQeBDs05k=; h=From:To:Cc:Subject:Date:From; b=RtQ5ZvbyYZM5FJxlOr7NGiYp8QgF5n5/pTzTETdflQszp3VR74fIe0x0bk7Un5sFe HZ8mLCfHLprUpIhFMKTCClpgQVqQfrugR38x86MuEvAvyzDU6aMwxDLcxVsotOGso7 UACpv3LsjiXz4anUjdIJH9/NSMXL50Q1qw/nxIm4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D629A60132 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Marc Zyngier , linux-kernel , linux-arm-kernel Subject: [PATCH v2] irqchip: gicv3-its: Don't assume GICv3 hardware supports 16bit INTID Date: Thu, 22 Jun 2017 12:44:52 -0500 Message-Id: <1498153492-30632-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170622_104535_688276_24CC55B5 X-CRM114-Status: GOOD ( 17.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Gleixner , Shanker Donthineni , Jason Cooper , Vikram Sethi MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The current ITS driver is assuming every ITS hardware implementation supports minimum of 16bit INTID. But this is not true, as per GICv3 specification, INTID field is IMPLEMENTATION DEFINED in the range of 14-24 bits. We might see an unpredictable system behavior on systems where hardware support less than 16bits and software tries to use 64K LPI interrupts. On Qualcomm Datacenter Technologies QDF2400 platform, boot log shows confusing information about number of LPI chunks as shown below. The QDF2400 ITS hardware supports 24bit INTID. This patch allocates the memory resources for PEND/PROP tables based on discoverable value which is specified in GITS_TYPER.IDbits. Also taking this opportunity to increase number of LPI/MSI(x) to 128K if the hardware is capable, and show log message that reflects the correct number of LPI chunks. ITS@0xff7efe0000: allocated 524288 Devices @3c0400000 (indirect, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Interrupt Collections @3c0130000 (flat, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Virtual CPUs @3c0140000 (flat, esz 8, psz 64K, shr 1) ITS: Allocated 524032 chunks for LPIs PCI/MSI: ITS@0xff7efe0000 domain created Platform MSI: ITS@0xff7efe0000 domain created Signed-off-by: Shanker Donthineni --- Changes since v1: No code changes, just rebase on tip of the Marc's branch and tested on QDF2400 platform. https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/irqchip-4.13 drivers/irqchip/irq-gic-v3-its.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index fee7d13..6000c56 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -691,9 +691,11 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) */ #define IRQS_PER_CHUNK_SHIFT 5 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) +#define ITS_MAX_LPI_NRBITS (17) /* 128K LPIs */ static unsigned long *lpi_bitmap; static u32 lpi_chunks; +static u32 lpi_nrbits; static DEFINE_SPINLOCK(lpi_lock); static int its_lpi_to_chunk(int lpi) @@ -789,26 +791,19 @@ static void its_lpi_free(struct event_lpi_map *map) } /* - * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to + * We allocate memory for PROPBASE to cover 2 ^ lpi_nrbits LPIs to * deal with (one configuration byte per interrupt). PENDBASE has to * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). */ -#define LPI_PROPBASE_SZ SZ_64K -#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) - -/* - * This is how many bits of ID we need, including the useless ones. - */ -#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) #define LPI_PROP_DEFAULT_PRIO 0xa0 static int __init its_alloc_lpi_tables(void) { + u32 size = ALIGN(BIT(lpi_nrbits), SZ_64K); phys_addr_t paddr; - gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, - get_order(LPI_PROPBASE_SZ)); + gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, get_order(size)); if (!gic_rdists->prop_page) { pr_err("Failed to allocate PROPBASE\n"); return -ENOMEM; @@ -820,10 +815,10 @@ static int __init its_alloc_lpi_tables(void) /* Priority 0xa0, Group-1, disabled */ memset(page_address(gic_rdists->prop_page), LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, - LPI_PROPBASE_SZ); + size); /* Make sure the GIC will observe the written configuration */ - gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); + gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), size); return 0; } @@ -1095,12 +1090,14 @@ static void its_cpu_init_lpis(void) pend_page = gic_data_rdist()->pend_page; if (!pend_page) { phys_addr_t paddr; + u32 size; /* - * The pending pages have to be at least 64kB aligned, - * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. + * The pending pages have to be at least 64kB aligned + * hence the 'ALIGN(BIT(lpi_nrbits)/8, SZ_64K)' below. */ + size = ALIGN(BIT(lpi_nrbits)/8, SZ_64K); pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, - get_order(max(LPI_PENDBASE_SZ, SZ_64K))); + get_order(size)); if (!pend_page) { pr_err("Failed to allocate PENDBASE for CPU%d\n", smp_processor_id()); @@ -1108,7 +1105,7 @@ static void its_cpu_init_lpis(void) } /* Make sure the GIC will observe the zero-ed page */ - gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); + gic_flush_dcache_to_poc(page_address(pend_page), size); paddr = page_to_phys(pend_page); pr_info("CPU%d: using LPI pending table @%pa\n", @@ -1130,7 +1127,7 @@ static void its_cpu_init_lpis(void) val = (page_to_phys(gic_rdists->prop_page) | GICR_PROPBASER_InnerShareable | GICR_PROPBASER_RaWaWb | - ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); + ((lpi_nrbits - 1) & GICR_PROPBASER_IDBITS_MASK)); gicr_write_propbaser(val, rbase + GICR_PROPBASER); tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); @@ -1900,9 +1897,10 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, return -ENXIO; } + lpi_nrbits = min_t(u32, rdists->id_bits, ITS_MAX_LPI_NRBITS); gic_rdists = rdists; its_alloc_lpi_tables(); - its_lpi_init(rdists->id_bits); + its_lpi_init(lpi_nrbits); return 0; }