From patchwork Sat Jun 24 03:38:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xie XiuQi X-Patchwork-Id: 9807571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7C9576032A for ; Sat, 24 Jun 2017 03:39:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6FFAD2866F for ; Sat, 24 Jun 2017 03:39:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63E65287DA; Sat, 24 Jun 2017 03:39:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C57702866F for ; Sat, 24 Jun 2017 03:39:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=nYZDMLENAAhDKcwxuuXyef225FH5F9V8osstksd1I7o=; b=ebTdwlrVpGhjNF jrRfhRw+8wl72Qn2USNdGDge74uwnM239emXXaHopLvY9UUYt9y9oz2vG3h132DZkRUYBiLkDRkqS D8uEC8SXfndDN8KtXtxxmJAz345Q0Krp5XZmMNte9cysOwox697whnWZ5w7PjKAAUmVpzrSbslfeD jpSWpn7xnJuNS+z96YIkc6+GhGEhpSShSRjKzNsrJ9IPanZnq48WnW5EviKbrn+UgB/TYjDHBqJo7 m6YyFXdQRZKbGXgjmHacY/b9SAzNRDr7uhg8itHSnYL7rNoQ1qMQ9WHXk7f4zOnBMo8X9fGMMhdQc TStdtLrjCsYxLKt+mXyQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dObvG-0008K5-4U; Sat, 24 Jun 2017 03:39:46 +0000 Received: from szxga03-in.huawei.com ([45.249.212.189]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dObvB-0008J5-MX for linux-arm-kernel@lists.infradead.org; Sat, 24 Jun 2017 03:39:44 +0000 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APY46812; Sat, 24 Jun 2017 11:39:09 +0800 (CST) Received: from localhost.localdomain.localdomain (10.175.113.25) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Sat, 24 Jun 2017 11:39:01 +0800 From: Xie XiuQi To: , , , Subject: [PATCH v5] trace: ras: add ARM processor error information trace event Date: Sat, 24 Jun 2017 11:38:23 +0800 Message-ID: <1498275503-137890-1-git-send-email-xiexiuqi@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.113.25] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.594DDEDE.004F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f5551e02e68cdd0dc8a76a0cd9c97366 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170623_203942_290685_F0925503 X-CRM114-Status: GOOD ( 13.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xiexiuqi@huawei.com, bristot@redhat.com, ard.biesheuvel@linaro.org, linux-kernel@vger.kernel.org, fu.wei@linaro.org, zhengqiang10@huawei.com, wangxiongfeng2@huawei.com, linux-arm-kernel@lists.infradead.org, shiju.jose@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new trace event for ARM processor error information, so that the user will know what error occurred. With this information the user may take appropriate action. These trace events are consistent with the ARM processor error information table which defined in UEFI 2.6 spec section N.2.4.4.1. --- v5: add trace enabled condition which is lost on v4 back again put flag after the type to keep multiple_error on a 2 byte boundary v4: use __print_flags instead of __print_symbolic, because ARM_PROC_ERR_FLAGS might have more than on bit set. setting up default values for __entry to avoid a lot of else branches. set flags to 0 by default instead of ~0. fix a typo rename arm_proc_err to arm_err_info_event remove "ARM Processor Error: " prefix rebase on Tyler's patchset v17 "Add UEFI 2.6 and ACPI 6.1 updates for RAS on ARM64" https://patchwork.kernel.org/patch/9806267/ v3: no change v2: add trace enabled condition as Steven's suggestion. fix a typo. https://patchwork.kernel.org/patch/9653767/ --- Cc: Steven Rostedt Cc: Tyler Baicar Signed-off-by: Xie XiuQi --- drivers/ras/ras.c | 11 +++++++ include/linux/cper.h | 5 ++++ include/ras/ras_event.h | 79 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index 39701a5..f76ab0f 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -22,7 +22,17 @@ void log_non_standard_event(const uuid_le *sec_type, const uuid_le *fru_id, void log_arm_hw_error(struct cper_sec_proc_arm *err) { + int i; + struct cper_arm_err_info *err_info; + trace_arm_event(err); + + if (!trace_arm_err_info_event_enabled()) + return; + + err_info = (struct cper_arm_err_info *)(err + 1); + for (i = 0; i < err->err_info_num; i++, err_info++) + trace_arm_err_info_event(err_info); } static int __init ras_init(void) @@ -42,6 +52,7 @@ static int __init ras_init(void) EXPORT_TRACEPOINT_SYMBOL_GPL(mc_event); EXPORT_TRACEPOINT_SYMBOL_GPL(non_standard_event); EXPORT_TRACEPOINT_SYMBOL_GPL(arm_event); +EXPORT_TRACEPOINT_SYMBOL_GPL(arm_err_info_event); int __init parse_ras_param(char *str) { diff --git a/include/linux/cper.h b/include/linux/cper.h index 4c671fc..17546bf 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -275,6 +275,11 @@ enum { #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) +#define CPER_ARM_INFO_TYPE_CACHE 0 +#define CPER_ARM_INFO_TYPE_TLB 1 +#define CPER_ARM_INFO_TYPE_BUS 2 +#define CPER_ARM_INFO_TYPE_UARCH 3 + /* * All tables and structs must be byte-packed to match CPER * specification, since the tables are provided by the system BIOS diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 429f46f..dd91ba8 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -206,6 +206,85 @@ __entry->running_state, __entry->psci_state) ); +#define ARM_PROC_ERR_TYPE \ + EM ( CPER_ARM_INFO_TYPE_CACHE, "cache error" ) \ + EM ( CPER_ARM_INFO_TYPE_TLB, "TLB error" ) \ + EM ( CPER_ARM_INFO_TYPE_BUS, "bus error" ) \ + EMe ( CPER_ARM_INFO_TYPE_UARCH, "micro-architectural error" ) + +/* + * First define the enums in MM_ACTION_RESULT to be exported to userspace + * via TRACE_DEFINE_ENUM(). + */ +#undef EM +#undef EMe +#define EM(a, b) TRACE_DEFINE_ENUM(a); +#define EMe(a, b) TRACE_DEFINE_ENUM(a); + +ARM_PROC_ERR_TYPE + +/* + * Now redefine the EM() and EMe() macros to map the enums to the strings + * that will be printed in the output. + */ +#undef EM +#undef EMe +#define EM(a, b) { a, b }, +#define EMe(a, b) { a, b } + +#define show_proc_err_flags(flags) __print_flags(flags, "|", \ + { CPER_ARM_INFO_FLAGS_FIRST, "First error captured" }, \ + { CPER_ARM_INFO_FLAGS_LAST, "Last error captured" }, \ + { CPER_ARM_INFO_FLAGS_PROPAGATED, "Propagated" }, \ + { CPER_ARM_INFO_FLAGS_OVERFLOW, "Overflow" }) + +TRACE_EVENT(arm_err_info_event, + + TP_PROTO(const struct cper_arm_err_info *err), + + TP_ARGS(err), + + TP_STRUCT__entry( + __field(u8, type) + __field(u8, flags) + __field(u16, multiple_error) + __field(u64, error_info) + __field(u64, virt_fault_addr) + __field(u64, physical_fault_addr) + ), + + TP_fast_assign( + __entry->type = err->type; + memset(&__entry->flags, 0, + sizeof(*__entry) - offsetof(typeof(*__entry), flags)); + __entry->multiple_error = ~0; + + if (err->validation_bits & CPER_ARM_INFO_VALID_MULTI_ERR) + __entry->multiple_error = err->multiple_error; + + if (err->validation_bits & CPER_ARM_INFO_VALID_FLAGS) + __entry->flags = err->flags; + + if (err->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) + __entry->error_info = err->error_info; + + if (err->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR) + __entry->virt_fault_addr = err->virt_fault_addr; + + if (err->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR) + __entry->physical_fault_addr = err->physical_fault_addr; + ), + + TP_printk("type: %s; count: %u; flags: %s;" + " error info: %016llx; virtual address: %016llx;" + " physical address: %016llx", + __print_symbolic(__entry->type, ARM_PROC_ERR_TYPE), + __entry->multiple_error, + show_proc_err_flags(__entry->flags), + __entry->error_info, __entry->virt_fault_addr, + __entry->physical_fault_addr) +); + /* * Non-Standard Section Report *