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Mon, 17 Jul 2017 23:44:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500335047; bh=AWmDwsp6duw+1NyTmXkeBLYqRlg1EQzi0aEW+0TaKxI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eOam3MU0JKJOJcAFM8G/OgaHf7Vi/7mLpI/Ju+beF1AvOeXTAGcJMgzOj/OBbvQaz Ntx9TbJMxelWk2KGzxnEC8OLz7IEt3d2FDwAyGuCPUcjL6Uw1rRlP1uVTJ1q36LESA ZHLRD9nPeBP1i3eT988IOR/aBUWeMZZPICAwnvvY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9BEFC607EF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: andy.gross@linaro.org, david.brown@linaro.org, Linus Walleij , Bjorn Andersson , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] [v2] pinctrl: qcom: disable GPIO groups with no pins Date: Mon, 17 Jul 2017 18:44:00 -0500 Message-Id: <1500335041-32711-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500335041-32711-1-git-send-email-timur@codeaurora.org> References: <1500335041-32711-1-git-send-email-timur@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170717_164427_648877_4CEC76A4 X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: timur@codeaurora.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To support sparse GPIO maps, pinctrl-msm client drivers can specify that a given GPIO has a pin count of zero. These GPIOs will be considered "hidden". Any attempt to claim the GPIO will fail, and they will not be listed in debugfs. Signed-off-by: Timur Tabi --- drivers/pinctrl/qcom/pinctrl-msm.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 273badd..d0f09a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -494,6 +494,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, }; g = &pctrl->soc->groups[offset]; + + /* If the GPIO group has no pins, then don't show it. */ + if (!g->npins) + return; + ctl_reg = readl(pctrl->regs + g->ctl_reg); is_out = !!(ctl_reg & BIT(g->oe_bit)); @@ -503,7 +508,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); + seq_printf(s, " %s\n", pulls[pull]); } static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -511,23 +516,30 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned gpio = chip->base; unsigned i; - for (i = 0; i < chip->ngpio; i++, gpio++) { + for (i = 0; i < chip->ngpio; i++, gpio++) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } } #else #define msm_gpio_dbg_show NULL #endif +/* If the GPIO has no pins, then treat it as unavailable. */ +static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + return g->npins ? 0 : -ENODEV; +} + static struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, .set = msm_gpio_set, - .request = gpiochip_generic_request, + .request = msm_gpio_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, };