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Tue, 08 Aug 2017 04:05:40 -0700 (PDT) X-Received: by 10.28.220.133 with SMTP id t127mr2570647wmg.12.1502190340553; Tue, 08 Aug 2017 04:05:40 -0700 (PDT) Received: from buildbot.pitowers.org ([217.33.127.173]) by smtp.gmail.com with ESMTPSA id 9sm1396198wmo.35.2017.08.08.04.05.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Aug 2017 04:05:40 -0700 (PDT) From: Phil Elwell To: Eric Anholt , Stefan Wahren , Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: bcm2836: Send event when onlining other cores Date: Tue, 8 Aug 2017 12:04:55 +0100 Message-Id: <1502190295-53391-2-git-send-email-phil@raspberrypi.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502190295-53391-1-git-send-email-phil@raspberrypi.org> References: <1502190295-53391-1-git-send-email-phil@raspberrypi.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-08-08_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_notspam policy=outbound_spam score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1706020000 definitions=main-1708080177 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170808_040607_145857_D2A98A93 X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Phil Elwell MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Secondary cores should enter a low-power idle state when waiting to be started. The "wfe" instruction causes a core to wait until an event or interrupt arrives before continuing to the next instruction, and the "sev" instruction sends a wakeup event to the other cores. Add an "sev" (and a memory barrier) to bcm2836_boot_secondary, the function that wakes the waiting cores during booting. This is required if the secondary cores are sitting in "wfe", and harmless if not. Signed-off-by: Phil Elwell --- arch/arm/mach-bcm/platsmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index 3fa1a99..7811160 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -312,6 +312,9 @@ static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle) writel(virt_to_phys(secondary_startup), intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu); + dsb(sy); + sev(); + iounmap(intc_base); return 0;