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Wed, 16 Aug 2017 10:45:52 -0700 (PDT) Received: from lbrmn-lnxub113.ric.broadcom.com ([192.19.224.250]) by smtp.gmail.com with ESMTPSA id w28sm949819qta.33.2017.08.16.10.45.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 16 Aug 2017 10:45:51 -0700 (PDT) From: Scott Branden To: Greg Kroah-Hartman Subject: [PATCH 2/3] w1: d1w: Provide callback for ds1wm read/write Date: Wed, 16 Aug 2017 10:45:24 -0700 Message-Id: <1502905525-5646-3-git-send-email-scott.branden@broadcom.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1502905525-5646-1-git-send-email-scott.branden@broadcom.com> References: <1502905525-5646-1-git-send-email-scott.branden@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170816_104613_834732_EE54E05E X-CRM114-Status: GOOD ( 11.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shreesha Rajashekar , BCM Kernel Feedback , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Scott Branden MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shreesha Rajashekar DS1WM core registers are accessed by reading from and writing to a group of registers in iproc SOC's. By default the read and write function uses __raw_readb() and __raw_writeb(), which wouldnt work for iproc. hence modifying to provide callbacks for read and write functions. Signed-off-by: Shreesha Rajashekar Signed-off-by: Scott Branden --- drivers/w1/masters/ds1wm.c | 18 ++++++++++++++++-- include/linux/mfd/ds1wm.h | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c index fd2e9da..9fadc39 100644 --- a/drivers/w1/masters/ds1wm.c +++ b/drivers/w1/masters/ds1wm.c @@ -115,12 +115,26 @@ struct ds1wm_data { static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg, u8 val) { - __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift)); + struct device *dev = &ds1wm_data->pdev->dev; + struct ds1wm_driver_data *pdata = dev_get_platdata(dev); + + if (pdata->write) + pdata->write(ds1wm_data->map, reg, val); + else + __raw_writeb(val, ds1wm_data->map + + (reg << ds1wm_data->bus_shift)); } static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg) { - return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift)); + struct device *dev = &ds1wm_data->pdev->dev; + struct ds1wm_driver_data *pdata = dev_get_platdata(dev); + + if (pdata->read) + return pdata->read(ds1wm_data->map, reg); + else + return __raw_readb(ds1wm_data->map + + (reg << ds1wm_data->bus_shift)); } diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h index 38a372a..c2d41d3 100644 --- a/include/linux/mfd/ds1wm.h +++ b/include/linux/mfd/ds1wm.h @@ -10,4 +10,6 @@ struct ds1wm_driver_data { /* ds1wm implements the precise timings of*/ /* a reset pulse/presence detect sequence.*/ unsigned int reset_recover_delay; + void (*write)(void __iomem *map, u32 reg, u8 val); + u8 (*read)(void __iomem *map, u32 reg); };