From patchwork Tue Aug 22 08:07:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 9914573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 485C3600C5 for ; Tue, 22 Aug 2017 08:21:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4915528809 for ; Tue, 22 Aug 2017 08:21:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3DF7028830; Tue, 22 Aug 2017 08:21:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_LOW autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9A93828809 for ; Tue, 22 Aug 2017 08:21:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qtelMcZxZQkN5UCy8iWrShkDfQ9Fvd/py9WlW+bGDso=; b=s01yp4HwOs1GbI ZCt5oLTYEFlLSsWw1jM6JGga/pS/H5qdEa8u1cGk6K/l8v95Sxt9BLBIdoLo/W3VqrU0qzqbqn2F/ F3yjJnqHfm4OX0ITX8/kNpqnZKRz3oGOn41COTabXuAp+xCf0EwEmYzw/5FcB2rUY7dZ3mmxwjNkm 7E4FBYYatnwLLoMptrLofuzlD8SadliNGveBtUwHsfocHuaCJCKMwnMl/6yiz1X4yRTwBTLUDP+xw E/hNMJMCAUaaPhumJIhKzldhBFju46lYPqqBEYlMI2WO453PiJYikt7ikdPdWYI+g8sjQ0Fw9dpMo pjRdy7rizvdsF2UW0haQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dk4RH-00062u-2x; Tue, 22 Aug 2017 08:21:31 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dk4QT-00053g-HK for linux-arm-kernel@bombadil.infradead.org; Tue, 22 Aug 2017 08:20:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Uvp89lsdoiN1lMPSdktKnR1fupwJugjFGWlLgS0483s=; b=ukLq2SqniTU/iW5Vf/DlzIzkS fI+aq3u23bzNt8hXhFPJ82/SbayZqZIXI6xPa3Sc4e3VOHtJjypas7iWAdgI1FZe+6qKjzWI1si/C Jmv2k6BHnLpkcMWQT5qFm8H+yeShAR/b8Zf312BKp5/R4A01HD27AkRvVD2k/B5vDfPfdOUTbarsL AF5Uu1zVVqpgKue8zQea3f/IorS4jOKBv7qM6h59u8xZP+JxVF+99gslOdeWK85gKhDquzHPKVIXo rhieVNzw4S/4cqgGSPuWDfnPaXiVArBX0qyPoBK7a2PrLlaRwai+PBHXbjkbUmVI8Sy3DcPovtZXU caC1ln01Q==; Received: from szxga04-in.huawei.com ([45.249.212.190]) by casper.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dk4JR-00063C-Dl for linux-arm-kernel@lists.infradead.org; Tue, 22 Aug 2017 08:13:27 +0000 Received: from 172.30.72.60 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFQ43985; Tue, 22 Aug 2017 16:08:26 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.301.0; Tue, 22 Aug 2017 16:08:15 +0800 From: Shaokun Zhang To: , Subject: [PATCH v5 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver Date: Tue, 22 Aug 2017 16:07:52 +0800 Message-ID: <1503389277-134131-2-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1503389277-134131-1-git-send-email-zhangshaokun@hisilicon.com> References: <1503389277-134131-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.599BE67A.00AA, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4e984155e31fe098526d465b0b3ce26c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170822_091326_181595_589F9E03 X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, linuxarm@huawei.com, linux-kernel@vger.kernel.org, Shaokun Zhang , Anurup M , jonathan.cameron@huawei.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation for the uncore PMUs on HiSilicon SoC. Reviewed-by: Jonathan Cameron Signed-off-by: Shaokun Zhang Signed-off-by: Anurup M --- Documentation/perf/hisi-pmu.txt | 53 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 0000000..267a028 --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,53 @@ +HiSilicon SoC uncore Performance Monitoring Unit (PMU) +====================================================== +The HiSilicon SoC chip includes various independent system device PMUs +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are +independent and have hardware logic to gather statistics and performance +information. + +The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster +(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. + +HiSilicon SoC uncore PMU driver +--------------------------------------- +Each device PMU has separate registers for event counting, control and +interrupt, and the PMU driver shall register perf PMU drivers like L3C, +HHA and DDRC etc. The available events and configuration options shall +be described in the sysfs, see : +/sys/devices/hisi_sccl{X}_/, or +/sys/bus/event_source/devices/hisi_sccl{X}_. +The "perf list" command shall list the available events from sysfs. + +Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU +name will appear in event listing as hisi_sccl_module. +where "sccl-id" is the identifier of the SCCL and "index-id" is the index of +module. +e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in +SCCL ID #3. +e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in +SCCL ID #1. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] +------------------------------------------ +hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] +------------------------------------------ +hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] +------------------------------------------ +hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] +------------------------------------------ + +$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 +$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 + +The current driver does not support sampling. So "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed.