From patchwork Thu Aug 31 08:20:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xie Yisheng X-Patchwork-Id: 9931551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A16CE602F0 for ; Thu, 31 Aug 2017 08:30:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8FE082889C for ; Thu, 31 Aug 2017 08:30:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 83C82288A2; Thu, 31 Aug 2017 08:30:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_LOW autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38F6B2889C for ; Thu, 31 Aug 2017 08:30:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OjrlnJQ3ECGGNNEHZmwLRH+sLmROmq7vDLjsvkK8dE0=; b=uTmePGGtXTEPIH 7Gw6x2CBjykaJ+/nO0s2Z1h/aRrjCWi+dAaAVCkGc5AzjY6UQ6BgJjPg+Jl8k/0JWCbGhacX9i5OU IUlN+vpuFavgzE7dCothGd7ZhhyR5JTAlVKw5rQbrV7It7GaIGAAvk+Y+XsSHuUXl5W9JflfrJOcQ 07eZZGmrChwmCP/eWM5ft19fvhLgRV1CwJOPwm5XZ7fbYo+QHh4AKsHseX+vnxMtOVoJPXWKZPORq 30OW4tbZtWjVXLDK3VlK5tyrhj5GOD+4r7thpooryRlNX8hajgs9uk2RqYXi7uMyeSoLKPK3x+lHx crSh/bmLrRq88Qopyq8g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dnKrU-0002PB-0N; Thu, 31 Aug 2017 08:30:04 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dnKrO-0002E5-Ib for linux-arm-kernel@lists.infradead.org; Thu, 31 Aug 2017 08:30:00 +0000 Received: from 172.30.72.60 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DGG21835; Thu, 31 Aug 2017 16:29:14 +0800 (CST) Received: from linux-ibm.site (10.175.102.37) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.301.0; Thu, 31 Aug 2017 16:29:05 +0800 From: Yisheng Xie To: Subject: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S Date: Thu, 31 Aug 2017 16:20:42 +0800 Message-ID: <1504167642-14922-7-git-send-email-xieyisheng1@huawei.com> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1504167642-14922-1-git-send-email-xieyisheng1@huawei.com> References: <1504167642-14922-1-git-send-email-xieyisheng1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.102.37] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A010201.59A7C8DB.0026, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b0b1ffa4171ef605925deb08e3654992 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170831_012959_035392_04B74E50 X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, lv.zheng@intel.com, will.deacon@arm.com, joro@8bytes.org, liubo95@huawei.com, rjw@rjwysocki.net, robert.moore@intel.com, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, robh+dt@kernel.org, hanjun.guo@linaro.org, xieyisheng@huawei.com, sudeep.holla@arm.com, chenjiankang1@huawei.com, devel@acpica.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, lenb@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which means we should not disable stall mode if stall/terminate mode is not configuable. Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which means if stall mode is force we should always set CD.S. This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use TERMINATE feature checking to ensue above ILLEGAL cases from happening. Signed-off-by: Yisheng Xie --- drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index dbda2eb..0745522 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -55,6 +55,7 @@ #define IDR0_STALL_MODEL_SHIFT 24 #define IDR0_STALL_MODEL_MASK 0x3 #define IDR0_STALL_MODEL_STALL (0 << IDR0_STALL_MODEL_SHIFT) +#define IDR0_STALL_MODEL_NS (1 << IDR0_STALL_MODEL_SHIFT) #define IDR0_STALL_MODEL_FORCE (2 << IDR0_STALL_MODEL_SHIFT) #define IDR0_TTENDIAN_SHIFT 21 #define IDR0_TTENDIAN_MASK 0x3 @@ -766,6 +767,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_SVM (1 << 15) #define ARM_SMMU_FEAT_HA (1 << 16) #define ARM_SMMU_FEAT_HD (1 << 17) +#define ARM_SMMU_FEAT_TERMINATE (1 << 18) u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) @@ -1402,6 +1404,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, u64 val; bool cd_live; __u64 *cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid); + struct arm_smmu_device *smmu = smmu_domain->smmu; /* * This function handles the following cases: @@ -1468,9 +1471,11 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, CTXDESC_CD_0_V; /* - * FIXME: STALL_MODEL==0b10 && CD.S==0 is ILLEGAL + * STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */ - if (ssid && smmu_domain->s1_cfg.can_stall) + if ((ssid && smmu_domain->s1_cfg.can_stall) || + (!(smmu->features & ARM_SMMU_FEAT_TERMINATE) && + smmu->features & ARM_SMMU_FEAT_STALLS)) val |= CTXDESC_CD_0_S; cdptr[0] = cpu_to_le64(val); @@ -1690,12 +1695,13 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, dst[1] |= STRTAB_STE_1_PPAR; /* - * FIXME: it is illegal to set S1STALLD if STALL_MODEL=0b10 - * (force). But according to the spec, it *must* be set for + * According to spec, it is illegal to set S1STALLD if + * STALL_MODEL is not 0b00. And it *must* be set for * devices that aren't capable of stalling (notably pci!) - * So we need a "STALL_MODEL=0b00" feature bit. */ - if (smmu->features & ARM_SMMU_FEAT_STALLS && !ste->can_stall) + if (smmu->features & ARM_SMMU_FEAT_STALLS && + smmu->features & ARM_SMMU_FEAT_TERMINATE && + !ste->can_stall) dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); val |= (s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK @@ -4577,9 +4583,13 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) switch (reg & IDR0_STALL_MODEL_MASK << IDR0_STALL_MODEL_SHIFT) { case IDR0_STALL_MODEL_STALL: + smmu->features |= ARM_SMMU_FEAT_TERMINATE; /* Fallthrough */ case IDR0_STALL_MODEL_FORCE: smmu->features |= ARM_SMMU_FEAT_STALLS; + break; + case IDR0_STALL_MODEL_NS: + smmu->features |= ARM_SMMU_FEAT_TERMINATE; } if (reg & IDR0_S1P)