From patchwork Tue Dec 5 16:13:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 10093241 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E4D096035E for ; Tue, 5 Dec 2017 15:32:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD831299BF for ; Tue, 5 Dec 2017 15:32:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DAC74299E5; Tue, 5 Dec 2017 15:32:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7122629C66 for ; Tue, 5 Dec 2017 15:31:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fAYLJnuAV4vTqs/b09XWBvtQxkcpq78ySa+lXariSN4=; b=etfsBXXYuQF/FG 5ffjfbHbDKWV4qTNC8h2xmliAse3O8yU8dWbZNZv5zYdAQEQo/g37I7H5Qj6m+4Hk0W/1Hwf04652 MK8yl8WUBVkK/g8nOmWCp1Ge5QC2XMTw5y/XOm6Cx2n0Edyho2Pg3YcfnCunD0SEVvC0U9C8lGZCj f70G35dDipccsjH5hqheXf/KKqZbcipXuboMtc8bovW0ObxCKtImTSRR8T4gwGFJXku1qvHzv6+7S +QRoPSWLJBS7cdtQxNa5m/+y1UtZ4sk1TtVa/RNzgIkgreYeISpLt1NIUxVHs7oB4yAejPZmiUoVl 2TsvtOsdDgOBv4ra6S7A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eMFCJ-000178-Kn; Tue, 05 Dec 2017 15:31:51 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eMFCF-0000qG-N2 for linux-arm-kernel@lists.infradead.org; Tue, 05 Dec 2017 15:31:49 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 33717EF25C6D2; Tue, 5 Dec 2017 23:31:08 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 5 Dec 2017 23:31:04 +0800 From: John Garry To: , , , , , , , , , , , Subject: [RFC PATCH 4/5] perf vendor events arm64: relocate thunderx2 JSON Date: Wed, 6 Dec 2017 00:13:18 +0800 Message-ID: <1512490399-94107-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512490399-94107-1-git-send-email-john.garry@huawei.com> References: <1512490399-94107-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171205_073148_059488_BB9E68A5 X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Garry , linux-kernel@vger.kernel.org, xuwei5@hisilicon.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Since the pmu events architecture folder structure supports arch/vendor/platform structure, relocate the ThunderX2 JSON. Also since Cavium ThunderX2 has implemented its events according to ARM recommendation, remove the fields apart from "EventCode". Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2-imp-def.json | 62 ---------------------- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 32 +++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +- 3 files changed, 33 insertions(+), 63 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json deleted file mode 100644 index 2db45c4..0000000 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json +++ /dev/null @@ -1,62 +0,0 @@ -[ - { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", - }, - { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", - }, - { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", - }, - { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", - }, - { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", - }, - { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", - }, - { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", - } -] diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json new file mode 100644 index 0000000..99313eb --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -0,0 +1,32 @@ +[ + { + "EventCode": "0x40", + }, + { + "EventCode": "0x41", + }, + { + "EventCode": "0x42", + }, + { + "EventCode": "0x43", + }, + { + "EventCode": "0x4C", + }, + { + "EventCode": "0x4D", + }, + { + "EventCode": "0x4E", + }, + { + "EventCode": "0x4F", + }, + { + "EventCode": "0x60", + }, + { + "EventCode": "0x61", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 219d675..32fa0d1 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,4 +12,4 @@ # # #Family-model,Version,Filename,EventType -0x00000000420f5160,v1,cavium,core +0x00000000420f5160,v1,cavium/thunderx2,core