From patchwork Tue Dec 5 16:13:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 10093257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 15C3D6035E for ; Tue, 5 Dec 2017 15:34:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09A94298DD for ; Tue, 5 Dec 2017 15:34:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0735C298F9; Tue, 5 Dec 2017 15:34:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D0F3F29972 for ; Tue, 5 Dec 2017 15:33:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eFzsX9sQVU4/+IdYG0pptIEgTFMCUmxCVKgw8vjbaI8=; b=jf/wLazVx0a50a Yx4MyOcwivstnFI8K2YFLYg+s7nIX8przBN79mwOlW5pWAshoveMTMKnDmRF2jaoxGAhSwW8i3GBq 0ZTA0RfwpsD1nc5KjdrriBZF+gyeYIyHOK6AdVn3dKW0mw6z9l+Nnd98K45UhKxrKbY2mOc0oAUQ/ k4iX3rBH3CHv7VGzHafvrVwzmNjfhTLO4KT3yMpIsmYAC+/sBf1oCTH/bNoU2n5PyfKjAvSv30ZYH 94QY3YqNpbUsMlT1o//BG7fdDmqc7MGtOZPaqelBIHC3EPux/IYxQj2eiR1HCd8BBtj284vOyvrnJ Es5dTM0TZTnz8YVZnvcw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eMFE1-0002iB-Lo; Tue, 05 Dec 2017 15:33:37 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eMFCG-0000rq-Ku for linux-arm-kernel@lists.infradead.org; Tue, 05 Dec 2017 15:31:56 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9FAC58F833B8D; Tue, 5 Dec 2017 23:31:13 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Tue, 5 Dec 2017 23:31:04 +0800 From: John Garry To: , , , , , , , , , , , Subject: [RFC PATCH 5/5] perf vendor events arm64: add HiSilicon hip08 JSON Date: Wed, 6 Dec 2017 00:13:19 +0800 Message-ID: <1512490399-94107-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512490399-94107-1-git-send-email-john.garry@huawei.com> References: <1512490399-94107-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171205_073148_960205_7DE6FFD5 X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Garry , linux-kernel@vger.kernel.org, xuwei5@hisilicon.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add HiSilicon hip08 JSON. Since hip08 has its events implementated according to ARM recommendation, only add fields "EventCode" (where applicable - hip08 also has implemented some other custom events). Signed-off-by: John Garry Signed-off-by: Shaokun Zhang --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 122 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 123 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 0000000..94fde40 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,122 @@ +[ + { + "EventCode": "0x40", + }, + { + "EventCode": "0x41", + }, + { + "EventCode": "0x42", + }, + { + "EventCode": "0x43", + }, + { + "EventCode": "0x46", + }, + { + "EventCode": "0x47", + }, + { + "EventCode": "0x48", + }, + { + "EventCode": "0x4C", + }, + { + "EventCode": "0x4D", + }, + { + "EventCode": "0x4E", + }, + { + "EventCode": "0x4F", + }, + { + "EventCode": "0x50", + }, + { + "EventCode": "0x51", + }, + { + "EventCode": "0x52", + }, + { + "EventCode": "0x53", + }, + { + "EventCode": "0x56", + }, + { + "EventCode": "0x57", + }, + { + "EventCode": "0x58", + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 32fa0d1..9cc42da 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -13,3 +13,4 @@ # #Family-model,Version,Filename,EventType 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core