From patchwork Mon Dec 11 08:54:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 10104451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EABA6602A7 for ; Mon, 11 Dec 2017 08:55:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08705294D0 for ; Mon, 11 Dec 2017 08:56:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F165A294D4; Mon, 11 Dec 2017 08:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D5A8A294D0 for ; Mon, 11 Dec 2017 08:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=blYoU6+piUhDnzXtail1IEKD1CawcajquRuDyGzrgY8=; b=elyAkPYbLv82ce KVcdv7fAPGm9+TwM5prjCS3C7NCtNA1v6J256c9b7Cl9eumGUGd8GGn7U1bJW7AWWkH0R04KBOI0t OZyPYOdDLzxKJBUiPX8PZwl7/4zrsL58rhBCUAQ8ipL3sCkKlbi9uWMvuOtziYjksrmhC7B/NsNA+ LvltBn0Ouu0zm2uHbqLChPmTHfCezvOHa/nz5dTuUGGKbqstdF4UqYCCJOEhU42nQcKURgghTavH0 T/ST5E6P1UIjzbTIBTVxc1jrZVhFIbQSa87FPlYZ67+PudhAh3X7mgK/62A6+1GRWqge5S6hNIAby 7XJNoQUGa3OjjSQzMTwA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eOJsU-0004Rb-0w; Mon, 11 Dec 2017 08:55:58 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eOJsA-0004BC-D2 for linux-arm-kernel@lists.infradead.org; Mon, 11 Dec 2017 08:55:41 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vBB8sOI5022110; Mon, 11 Dec 2017 09:54:54 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2er7kg8hhu-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 11 Dec 2017 09:54:54 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4368938; Mon, 11 Dec 2017 08:54:52 +0000 (GMT) Received: from Webmail-eu.st.com (gpxdag3node5.st.com [10.75.127.72]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 95BAF249C; Mon, 11 Dec 2017 08:54:52 +0000 (GMT) Received: from localhost (10.75.127.46) by GPXDAG3NODE5.st.com (10.75.127.72) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 11 Dec 2017 09:54:52 +0100 From: Alexandre Torgue To: Maxime Coquelin , Linus Walleij , Rob Herring , Mark Rutland , Jonathan Corbet , Russell King Subject: [PATCH 5/5] ARM: dts: stm32: use dedicated files for pinctrl on stm32f7 family Date: Mon, 11 Dec 2017 09:54:35 +0100 Message-ID: <1512982475-32661-6-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512982475-32661-2-git-send-email-alexandre.torgue@st.com> References: <1512982475-32661-2-git-send-email-alexandre.torgue@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To GPXDAG3NODE5.st.com (10.75.127.72) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-12-11_03:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171211_005538_888624_73D899B2 X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, same stm32f746-pinctrl driver is used for stm32f746 and stm32f769 MCU. As pin map is different between those 2 MCUs, a stm32f769-pinctrl driver has been recently added. This patch -allows to use stm32f769-pinctrl driver for stm32f769 boards -reworks stm32 devicetree files to fit with stm32f746 / stm32f769 Signed-off-by: Alexandre Torgue diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 2d4e717..b2d4b8c 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" #include / { diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi new file mode 100644 index 0000000..4c66fa40 --- /dev/null +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + cec_pins_a: cec@0 { + pins { + pinmux = ; /* HDMI CEC */ + slew-rate = <0>; + drive-open-drain; + bias-disable; + }; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_pins_b: usart1@1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 4d85dba..623b6f2 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f746-pinctrl.dtsi" #include / { diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi new file mode 100644 index 0000000..f0e6309 --- /dev/null +++ b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f746-pinctrl"; +}; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 5f66d15..8fe96d6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -42,7 +42,6 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" -#include #include #include @@ -498,222 +497,6 @@ reg = <0x40007000 0x400>; }; - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f746-pinctrl"; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - cec_pins_a: cec@0 { - pins { - pinmux = ; /* HDMI CEC */ - slew-rate = <0>; - drive-open-drain; - bias-disable; - }; - }; - - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_pins_b: usart1@1 { - pins1 { - pinmux = ; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* USART1_RX */ - bias-disable; - }; - }; - - i2c1_pins_b: i2c1@0 { - pins { - pinmux = , /* I2C1 SDA */ - ; /* I2C1 SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs@0 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_b: usbotg-hs@1 { - pins { - pinmux = , /* OTG_HS_ULPI_NXT */ - , /* OTG_HS_ULPI_DIR */ - , /* OTG_HS_ULPI_STP */ - , /* OTG_HS_ULPI_CK */ - , /* OTG_HS_ULPI_D0 */ - , /* OTG_HS_ULPI_D1 */ - , /* OTG_HS_ULPI_D2 */ - , /* OTG_HS_ULPI_D3 */ - , /* OTG_HS_ULPI_D4 */ - , /* OTG_HS_ULPI_D5 */ - , /* OTG_HS_ULPI_D6 */ - ; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_a: usbotg-fs@0 { - pins { - pinmux = , /* OTG_FS_ID */ - , /* OTG_FS_DM */ - ; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - }; - crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 4463ca1..9dba286 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -42,11 +42,12 @@ /dts-v1/; #include "stm32f746.dtsi" +#include "stm32f769-pinctrl.dtsi" #include / { model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f7"; + compatible = "st,stm32f769-disco", "st,stm32f769"; chosen { bootargs = "root=/dev/ram"; diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi new file mode 100644 index 0000000..787da27 --- /dev/null +++ b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f769-pinctrl"; +};