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[46.246.40.247]) by smtp.googlemail.com with ESMTPSA id w21sm609188lfi.86.2018.01.09.04.51.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jan 2018 04:51:17 -0800 (PST) Message-ID: <1515502273.2493.9.camel@googlemail.com> Subject: [PATCH] ARM: i.MX6: add new silicon revision number 1.6 From: Christoph Fritz To: Shawn Guo Date: Tue, 09 Jan 2018 13:51:13 +0100 X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180109_045131_826346_117C586A X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: chf.fritz@googlemail.com Cc: Fabio Estevam , linux-arm-kernel , Sascha Hauer Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds new silicon revision number 1.6 as specified in document IMX6DQCEC.pdf. Signed-off-by: Christoph Fritz Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/anatop.c | 4 ++++ include/soc/imx/revision.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 649a84c..deb98b8 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -157,6 +157,10 @@ void __init imx_init_revision_from_anatop(void) */ revision = IMX_CHIP_REVISION_1_5; break; + case 6: + /* marked as 'E' in part number last character */ + revision = IMX_CHIP_REVISION_1_6; + break; default: /* * Fail back to return raw register value instead of 0xff. diff --git a/include/soc/imx/revision.h b/include/soc/imx/revision.h index 9ea3469..cd4c847 100644 --- a/include/soc/imx/revision.h +++ b/include/soc/imx/revision.h @@ -15,6 +15,7 @@ #define IMX_CHIP_REVISION_1_3 0x13 #define IMX_CHIP_REVISION_1_4 0x14 #define IMX_CHIP_REVISION_1_5 0x15 +#define IMX_CHIP_REVISION_1_6 0x16 #define IMX_CHIP_REVISION_2_0 0x20 #define IMX_CHIP_REVISION_2_1 0x21 #define IMX_CHIP_REVISION_2_2 0x22