From patchwork Tue Feb 6 17:45:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 10203517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF6D160247 for ; Tue, 6 Feb 2018 16:58:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB067288DE for ; Tue, 6 Feb 2018 16:58:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9FBD428A9D; Tue, 6 Feb 2018 16:58:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 39639288DE for ; Tue, 6 Feb 2018 16:58:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KzQ7JkZ0fFLSU5p6nfnxi4jh3DFnoHgh9YFrnEWkVOw=; b=tgGstITLBRIFUJ B1/zn7f+qnBZT4mNtMOIVnCbmCjvaNIk6P4mSC9whrxNEaQ9Ma7zWCUrTIEvGTyHSsmgz9SPPXxAD MagMdRlY5jdhXGLRg+he7YmdHgF1iR1i3+t1EKUnm4fucuKgSvjDon9EVx3KvpxVj6bgHicN8l2vS QwC054IPM8UtBCXPGGYYBg4+ql78lqxLzQHYa3iuvS5PR1v5DzacmEqXX85sWRalcmH4Swt+KqtAg cVTYsBbVQyIrR6a1Gb74wsPgmHo1ULJeacPVp7m0GYc35VJ3bIoAqAfiVLh3Lfo07Yv4hKx/b574b d//g+z93/lINHH+Bn3dw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1ej6ZV-00088h-8U; Tue, 06 Feb 2018 16:58:17 +0000 Received: from [45.249.212.35] (helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1ej6Xq-0006Ac-3q for linux-arm-kernel@lists.infradead.org; Tue, 06 Feb 2018 16:56:46 +0000 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id CFD39EE5CD1A; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:53 +0800 From: John Garry To: , , , , , , , , , Subject: [PATCH 9/9] perf utils: add HiSilicon hip08 JSON file Date: Wed, 7 Feb 2018 01:45:04 +0800 Message-ID: <1517939104-230881-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhangshaokun@hisilicon.com, John Garry , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. The brief description is kept for readability for arch defined events, but is not strictly required. Signed-off-by: John Garry --- .../arch/arm64/hisilicon/hip08/core-imp-def.json | 140 +++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 141 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json new file mode 100644 index 0000000..ca0be5e --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -0,0 +1,140 @@ +[ + { + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" + }, + { + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" + }, + { + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" + }, + { + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" + }, + { + "ArchStdEvent": "0x46", + "BriefDescription": "L1D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x47", + "BriefDescription": "L1D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x48", + "BriefDescription": "L1D cache invalidate" + }, + { + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D tlb refill, read" + }, + { + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" + }, + { + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" + }, + { + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" + }, + { + "ArchStdEvent": "0x50", + "BriefDescription": "L2D cache access, read" + }, + { + "ArchStdEvent": "0x51", + "BriefDescription": "L2D cache access, write" + }, + { + "ArchStdEvent": "0x52", + "BriefDescription": "L2D cache refill, read" + }, + { + "ArchStdEvent": "0x53", + "BriefDescription": "L2D cache refill, write" + }, + { + "ArchStdEvent": "0x56", + "BriefDescription": "L2D cache Write-Back, victim" + }, + { + "ArchStdEvent": "0x57", + "BriefDescription": "L2D cache Write-Back, cleaning and coherency" + }, + { + "ArchStdEvent": "0x58", + "BriefDescription": "L2D cache invalidate" + }, + { + "PublicDescription": "Level 1 instruction cache prefetch access count", + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count", + }, + { + "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count", + }, + { + "PublicDescription": "Instruction queue is empty", + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty", + }, + { + "PublicDescription": "Instruction fetch stall cycles", + "EventCode": "0x1044", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles", + }, + { + "PublicDescription": "Instructions can receive, but not send", + "EventCode": "0x2014", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions can receive, but not send", + }, + { + "PublicDescription": "Prefetch request from LSU", + "EventCode": "0x6013", + "EventName": "PRF_REQ", + "BriefDescription": "Prefetch request from LSU", + }, + { + "PublicDescription": "Hit on prefetched data", + "EventCode": "0x6014", + "EventName": "HIT_ON_PRF", + "BriefDescription": "Hit on prefetched data", + }, + { + "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "EventCode": "0x7004", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "EventCode": "0x7006", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + }, + { + "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + "EventCode": "0x7007", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index cf14e23..8f11aeb 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,3 +14,4 @@ #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core 0x00000000420f5160,v1,cavium/thunderx2,core +0x00000000480fd010,v1,hisilicon/hip08,core