From patchwork Tue Feb 27 21:29:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Kaiser X-Patchwork-Id: 10246107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9488C60362 for ; Tue, 27 Feb 2018 21:30:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82E9128AB4 for ; Tue, 27 Feb 2018 21:30:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 764CC28AB6; Tue, 27 Feb 2018 21:30:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E405E28AB4 for ; Tue, 27 Feb 2018 21:30:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=U8RftCAs58KaTadwuSIpn65uTROuqQCVPDqypfqx87Q=; b=ZMlkLvwkhQFPmJAdYJNcNun7EX Zn8SXhFCqdTkxFPRY4lWmNzRbVuSJpJOsH0+EJYi/d+0ytt7g5tBEotPErH++XoVQ3CmFsf7lmDoN oghu2Vv8FXgN58XBcpdFt75evv+sUEc0mBXrNQEa28K0RkLpo8b1xJQIbJuEzPh2rgU54Dy4ohdvr QH9gBpZyEoq6EEJJGcu7kCKv35WJwKoDGXzAaiuHdYNmbNSSN1tdg9rOq5bBXaiDO5d6NTbzwqogr JCewCVfh6Uq699u23wYlQSvAia6DFvZEYaLfd3/LzVjumAqYzYt9tIjq6qWCcAQp+inGjHjLubso8 as11y+vA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eqmox-0000jV-M1; Tue, 27 Feb 2018 21:29:59 +0000 Received: from botnar.kaiser.cx ([176.28.20.183]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1eqmot-0000hM-DO for linux-arm-kernel@lists.infradead.org; Tue, 27 Feb 2018 21:29:57 +0000 Received: from p4fdc8579.dip0.t-ipconnect.de ([79.220.133.121] helo=martin-debian-1.paytec.ch) by botnar.kaiser.cx with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.72) (envelope-from ) id 1eqmob-0001aZ-V2; Tue, 27 Feb 2018 22:29:38 +0100 From: Martin Kaiser To: Shawn Guo , Sascha Hauer , Fabio Estevam , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] ARM: imx: avic: set low-power interrupt mask for imx25 Date: Tue, 27 Feb 2018 22:29:15 +0100 Message-Id: <1519766955-4302-1-git-send-email-martin@kaiser.cx> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1518628894-8328-1-git-send-email-martin@kaiser.cx> References: <1518628894-8328-1-git-send-email-martin@kaiser.cx> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180227_132955_610536_B655A702 X-CRM114-Status: GOOD ( 16.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Kaiser MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP imx25 contains two registers (LPIMR0 and 1) to define which interrupts are enabled in low-power mode. As of today, those two registers are configured to enable all interrupts. Before going to low-power mode, the AVIC's INTENABLEH and INTENABLEL registers are configured to enable only those interrupts which are used as wakeup sources. It turned out that this approach is not sufficient if we want the imx25 to go into stop mode during suspend-to-ram. (Stop mode is the low-power mode that consumes the least power. The peripheral master clock is switched off in this mode). For stop mode to work, the LPIMR0 and 1 registers have to be configured with the set of interrupts that are allowed in low-power mode. Fortunately, the bits in the LPIMR registers are assigned to the same interrupts as the bits in INTENABLEH and INTENABLEL. However, LPIMR uses 1 to mask an interrupt whereas the INTENABLE registers use 1 to enable an interrupt. This patch sets the LPIMR registers to the inverted bitmask of the INTENABLE registers during suspend and goes back to "all interrupts masked" when we wake up again. We also make this the default at startup. As far as I know, the other supported imx architectures have no similar mechanism. Since the LPIMR registers are part of the CCM module, we query the device tree for an imx25 ccm node in order to detect if we're running on imx25. Signed-off-by: Martin Kaiser --- changes in v2 - keep declarations of avic_base and mx25_ccm_base separate - newlines before mx25-specific code arch/arm/mach-imx/avic.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index 1afccae..c0434a3 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -51,7 +52,12 @@ #define AVIC_NUM_IRQS 64 +/* low power interrupt mask registers */ +#define MX25_CCM_LPIMR0 0x68 +#define MX25_CCM_LPIMR1 0x6C + static void __iomem *avic_base; +static void __iomem *mx25_ccm_base; static struct irq_domain *domain; #ifdef CONFIG_FIQ @@ -93,6 +99,18 @@ static void avic_irq_suspend(struct irq_data *d) avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); imx_writel(gc->wake_active, avic_base + ct->regs.mask); + + if (mx25_ccm_base) { + u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? + MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; + /* + * The interrupts which are still enabled will be used as wakeup + * sources. Allow those interrupts in low-power mode. + * The LPIMR registers use 0 to allow an interrupt, the AVIC + * registers use 1. + */ + imx_writel(~gc->wake_active, mx25_ccm_base + offs); + } } static void avic_irq_resume(struct irq_data *d) @@ -102,6 +120,13 @@ static void avic_irq_resume(struct irq_data *d) int idx = d->hwirq >> 5; imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); + + if (mx25_ccm_base) { + u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? + MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; + + imx_writel(0xffffffff, mx25_ccm_base + offs); + } } #else @@ -158,6 +183,18 @@ void __init mxc_init_irq(void __iomem *irqbase) avic_base = irqbase; + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); + mx25_ccm_base = of_iomap(np, 0); + + if (mx25_ccm_base) { + /* + * By default, we mask all interrupts. We set the actual mask + * before we go into low-power mode. + */ + imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); + imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); + } + /* put the AVIC into the reset value with * all interrupts disabled */