| Message ID | 1521800336-19266-14-git-send-email-sricharan@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote: > Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++++++++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > index 6a838b5..dbca7ec 100644 > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts > @@ -21,6 +21,7 @@ > > aliases { > serial0 = &blsp1_uart5; > + serial1 = &serial_blsp2; > }; > > chosen { > @@ -41,6 +42,47 @@ > bias-disable; > }; > }; > + > + i2c_0_pins: i2c_0_pinmux { > + mux { > + pins = "gpio42", "gpio43"; > + function = "blsp1_i2c"; > + drive-strength = <8>; > + bias-disable; > + }; > + }; > + > + spi_0_pins: spi_0_pins { > + mux { > + pins = "gpio38", "gpio39", "gpio40", "gpio41"; > + function = "blsp0_spi"; > + drive-strength = <8>; > + bias-disable; > + }; > + }; > + > + hsuart_pins: hsuart_pins { > + mux { > + pins = "gpio46", "gpio47", "gpio48", "gpio49"; > + function = "blsp2_uart"; > + drive-strength = <8>; > + bias-disable; > + }; > + }; > + > + qpic_pins: qpic_pins { > + mux { > + pins = "gpio1", "gpio3", "gpio4", > + "gpio5", "gpio6", "gpio7", > + "gpio8", "gpio10", "gpio11", > + "gpio12", "gpio13", "gpio14", > + "gpio15", "gpio16", "gpio17"; > + function = "qpic"; I would prefer that you move the pinmux part to the same dtsi that defines the nand and add the board specific pinconf (electrical properties) here. That way we limit the repetition between the board files. > + drive-strength = <8>; > + bias-disable; > + }; > + }; > + > }; > Other than that, Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn
Hi Bjorn, On 3/27/2018 11:19 PM, Bjorn Andersson wrote: > On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote: > >> Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> >> Signed-off-by: Sricharan R <sricharan@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++++++++++++++++++++++++ >> 1 file changed, 103 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> index 6a838b5..dbca7ec 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts >> @@ -21,6 +21,7 @@ >> >> aliases { >> serial0 = &blsp1_uart5; >> + serial1 = &serial_blsp2; >> }; >> >> chosen { >> @@ -41,6 +42,47 @@ >> bias-disable; >> }; >> }; >> + >> + i2c_0_pins: i2c_0_pinmux { >> + mux { >> + pins = "gpio42", "gpio43"; >> + function = "blsp1_i2c"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> + >> + spi_0_pins: spi_0_pins { >> + mux { >> + pins = "gpio38", "gpio39", "gpio40", "gpio41"; >> + function = "blsp0_spi"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> + >> + hsuart_pins: hsuart_pins { >> + mux { >> + pins = "gpio46", "gpio47", "gpio48", "gpio49"; >> + function = "blsp2_uart"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> + >> + qpic_pins: qpic_pins { >> + mux { >> + pins = "gpio1", "gpio3", "gpio4", >> + "gpio5", "gpio6", "gpio7", >> + "gpio8", "gpio10", "gpio11", >> + "gpio12", "gpio13", "gpio14", >> + "gpio15", "gpio16", "gpio17"; >> + function = "qpic"; > > I would prefer that you move the pinmux part to the same dtsi that > defines the nand and add the board specific pinconf (electrical > properties) here. That way we limit the repetition between the board > files. > sure. will do. >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> + >> }; >> > > Other than that, > > Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Thanks. Again, thanks for your time and all the reviews. Regards, Sricharan
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 6a838b5..dbca7ec 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -21,6 +21,7 @@ aliases { serial0 = &blsp1_uart5; + serial1 = &serial_blsp2; }; chosen { @@ -41,6 +42,47 @@ bias-disable; }; }; + + i2c_0_pins: i2c_0_pinmux { + mux { + pins = "gpio42", "gpio43"; + function = "blsp1_i2c"; + drive-strength = <8>; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pins { + mux { + pins = "gpio38", "gpio39", "gpio40", "gpio41"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; + }; + + hsuart_pins: hsuart_pins { + mux { + pins = "gpio46", "gpio47", "gpio48", "gpio49"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + qpic_pins: qpic_pins { + mux { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17"; + function = "qpic"; + drive-strength = <8>; + bias-disable; + }; + }; + }; serial@78b3000 { @@ -48,5 +90,66 @@ pinctrl-names = "default"; status = "ok"; }; + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + serial@78b1000 { + pinctrl-0 = <&hsuart_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + i2c@78b6000 { + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + dma@7984000 { + status = "ok"; + }; + + nand@79b0000 { + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "ok"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; + }; + + phy@86000 { + status = "ok"; + }; + + phy@8e000 { + status = "ok"; + }; + + pci@20000000 { + status = "ok"; + perst-gpio = <&tlmm 58 0x1>; + }; + + pci@10000000 { + status = "ok"; + perst-gpio = <&tlmm 61 0x1>; + }; }; };