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Mon, 2 Apr 2018 17:48:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522691288; bh=KEbDxTqRnoli8BV6m7pSzTjmw92ch6lmjReUBG3d1hA=; h=From:To:Cc:Subject:Date:From; b=nVKbJih6GBFQbqd67q00ys0HLRA1a8S4hE9jJtBJh9yHN3erXBE29J//S2LNA/mK1 pEuRzMoRnW4y6NV3mzn0I+J2XmuFEorC2SMFX0hlG27ixANY/OWV7TMOqx/qmMaFvi JWd4ymVdRGjBd+sprpXC0tD+4gnND3yqazFSvv3I= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5F4E6601D3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-alpha@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org Subject: [PATCH] alpha: io: reorder barriers to guarantee writeX() and iowriteX() ordering Date: Mon, 2 Apr 2018 13:48:00 -0400 Message-Id: <1522691281-21593-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180402_104820_518390_98B01945 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kate Stewart , arnd@arndb.de, Greg Kroah-Hartman , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Sinan Kaya , Ivan Kokshaysky , Guenter Roeck , Philippe Ombredanne , Matt Turner , linux-arm-kernel@lists.infradead.org, Richard Henderson Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP memory-barriers.txt has been updated with the following requirement. "When using writel(), a prior wmb() is not needed to guarantee that the cache coherent memory writes have completed before writing to the MMIO region." Current writeX() and iowriteX() implementations on alpha are not satisfying this requirement as the barrier is after the register write. Move mb() in writeX() and iowriteX() functions to guarantee that HW observes memory changes before performing register operations. Signed-off-by: Sinan Kaya Reported-by: Arnd Bergmann --- arch/alpha/include/asm/io.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index d123ff9..4c533fc 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -341,14 +341,14 @@ extern inline unsigned int ioread16(void __iomem *addr) extern inline void iowrite8(u8 b, void __iomem *addr) { - IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr); mb(); + IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr); } extern inline void iowrite16(u16 b, void __iomem *addr) { - IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr); mb(); + IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr); } extern inline u8 inb(unsigned long port) @@ -382,8 +382,8 @@ extern inline unsigned int ioread32(void __iomem *addr) extern inline void iowrite32(u32 b, void __iomem *addr) { - IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr); mb(); + IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr); } extern inline u32 inl(unsigned long port) @@ -434,14 +434,14 @@ extern inline u16 readw(const volatile void __iomem *addr) extern inline void writeb(u8 b, volatile void __iomem *addr) { - __raw_writeb(b, addr); mb(); + __raw_writeb(b, addr); } extern inline void writew(u16 b, volatile void __iomem *addr) { - __raw_writew(b, addr); mb(); + __raw_writew(b, addr); } #endif @@ -482,14 +482,14 @@ extern inline u64 readq(const volatile void __iomem *addr) extern inline void writel(u32 b, volatile void __iomem *addr) { - __raw_writel(b, addr); mb(); + __raw_writel(b, addr); } extern inline void writeq(u64 b, volatile void __iomem *addr) { - __raw_writeq(b, addr); mb(); + __raw_writeq(b, addr); } #endif