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Wed, 4 Apr 2018 23:58:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886308; bh=o8TjFDYwffhmWD4rbtWynHXU54myXkNL915S7Ew1PF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tx9BIi2zgBlMFu7xAZMHKHxFAqnPpPamhrK3bVZI3p6nn7DNlNrm1YF7NftEBWklE wxOuxXIRtahwgJ1I6VY6Qd0z3lI/a9ZL3MSTlznue9mpleVVwC9Vruky67nqNna/6U wm91ua93EKv8mh0SusyGeBB9Ac4NYyFJeQyZCAKM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7BD0360F6E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Subject: [PATCH v3 3/5] io: define stronger ordering for the default writeX() implementation Date: Wed, 4 Apr 2018 19:58:18 -0400 Message-Id: <1522886301-25955-3-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> References: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180404_165836_965470_3BA667AB X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sinan Kaya , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The default implementation of mapping writeX() to __raw_writeX() is wrong. writeX() has stronger ordering semantics. Compiler is allowed to reorder memory writes against __raw_writeX(). Use the previously defined __io_aw() and __io_bw() macros to harden code generation according to architecture support. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index fc554af..ca268d9 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -207,7 +207,9 @@ static inline u64 readq(const volatile void __iomem *addr) #define writeb writeb static inline void writeb(u8 value, volatile void __iomem *addr) { + __io_bw(); __raw_writeb(value, addr); + __io_aw(); } #endif @@ -215,7 +217,9 @@ static inline void writeb(u8 value, volatile void __iomem *addr) #define writew writew static inline void writew(u16 value, volatile void __iomem *addr) { + __io_bw(); __raw_writew(cpu_to_le16(value), addr); + __io_aw(); } #endif @@ -223,7 +227,9 @@ static inline void writew(u16 value, volatile void __iomem *addr) #define writel writel static inline void writel(u32 value, volatile void __iomem *addr) { + __io_bw(); __raw_writel(__cpu_to_le32(value), addr); + __io_aw(); } #endif @@ -232,7 +238,9 @@ static inline void writel(u32 value, volatile void __iomem *addr) #define writeq writeq static inline void writeq(u64 value, volatile void __iomem *addr) { + __io_bw(); __raw_writeq(__cpu_to_le64(value), addr); + __io_aw(); } #endif #endif /* CONFIG_64BIT */