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Tue, 10 Apr 2018 20:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523390957; bh=hCbGorxGn+T4WAaTdaCKkEdjc7Xs/Z2rUxwuJu4YqeM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XkDWVBezXAN/hVunw2uZiYrLdykaCjRJwnqIlJPXsk/MTenylQojbzMQOoQhalJkh hyEMIhgIJqaKJQHwewQEpFcUJ2YFFuzIz4dZ/1Tw499tQ2C9SIc9t/IfqrWu66WpFP P4/fgpYavEdPOIHo6I015VMa/t9hyjBHo32wzCtk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 47DEF6081C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rishabhb@codeaurora.org From: Rishabh Bhatnagar To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc Date: Tue, 10 Apr 2018 13:08:12 -0700 Message-Id: <1523390893-10904-2-git-send-email-rishabhb@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org> References: <1523390893-10904-1-git-send-email-rishabhb@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180410_130928_837059_009DF689 X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tsoni@codeaurora.org, kyan@codeaurora.org, ckadabi@codeaurora.org, stanimir.varbanov@linaro.org, evgreen@chromium.org, linux-kernel@vger.kernel.org, Rishabh Bhatnagar , linux-arm@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar Reviewed-by: Evan Green --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..497cf0f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,58 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: must be addresses and sizes of the LLCC registers + +- #cache-cells: + Usage: required + Value Type: + Definition: Number of cache cells, must be 1 + +- max-slices: + usage: required + Value Type: + Definition: Number of cache slices supported by hardware + +Example: + + llcc: qcom,llcc@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + #cache-cells = <1>; + max-slices = <32>; + }; + +== Client == + +Properties: +- cache-slice-names: + Usage: required + Value type: + Definition: A set of names that identify the usecase names of a + client that uses cache slice. These strings are + used to look up the cache slice entries by name. + +- cache-slices: + Usage: required + Value type: + Definition: The tuple has phandle to llcc device as the first + argument and the second argument is the usecase + id of the client. +For Example: + venus { + cache-slice-names = "vidsc0", "vidsc1"; + cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>; + };