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Thu, 3 May 2018 11:53:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525348426; bh=Khio4yp18RP2qjtrW2IR4rI/BaagNKOKUltjQHeGTPA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UlCZMJ+2OI1PXNWXhE9AdoGORGy5psedqaINSAPf3csRA9C6FyXQ0DZaWIQZY0Yqo RTJi8EkKu7NJWau8Oy7jzkA9TdY+cxgcTMOs9jUuqw4j/hYlJzg+Y/ON7v+xzOmbYd Ir2vX3X0Ys0nU0lesdRprMeYHZwgGkKJU+mZcon0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DCD1D607E4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-clk@vger.kernel.org Subject: [PATCH v5 11/14] dt: qcom: Add SAW regulator for 8x96 CPUs Date: Thu, 3 May 2018 14:52:32 +0300 Message-Id: <1525348355-25471-12-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525348355-25471-1-git-send-email-ilialin@codeaurora.org> References: <1525348355-25471-1-git-send-email-ilialin@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180503_045358_680794_87E51163 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, tfinkel@codeaurora.org, ilialin@codeaurora.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 1. Add syscon node for the SAW CPU registers 2. Add SAW regulators gang definition for s8-s11 3. Add voltages to the OPP tables 4. Add the s11 SAW regulator as CPU regulator Signed-off-by: Ilia Lin --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 75 +++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e6cf290..d7adef9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. MSM8996"; @@ -99,6 +100,7 @@ reg = <0x0 0x0>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -114,6 +116,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -125,6 +128,7 @@ reg = <0x0 0x100>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -140,6 +144,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -174,66 +179,82 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; }; @@ -244,102 +265,127 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; }; @@ -656,6 +702,10 @@ #mbox-cells = <1>; }; + saw3: syscon@9A10000 { + compatible = "syscon"; + reg = <0x9A10000 0x1000>; + }; gcc: clock-controller@300000 { compatible = "qcom,gcc-msm8996"; #clock-cells = <1>; @@ -882,6 +932,31 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; + pmic@1 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + spm-regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <905000>; + regulator-max-microvolt = <1140000>; + }; + }; + }; }; mmcc: clock-controller@8c0000 {